Abstract
The new generation of video coding standard, Versatile Video Coding (VVC), reduces the code stream by 50% at the cost of huge computational complexity by comparison with High Efficiency Video Coding standard (HEVC), especially in the transform module. In order to alleviate the high computational complexity of VVC multiple transform selection (MTS) algorithm, a new high-performance VVC MTS hardware architecture based on field programmable gate array (FPGA) is proposed. In this paper, a pipelined MTS processor architecture is able to efficiently perform the one-dimensional (1-D) transform from 4 × 4 to 64 × 64 residual blocks. The architecture design takes advantages of parallel computing and time-division multiplexing to increase the reuse rate of hardware architecture and further enhance the speed performance. The proposed implementation in Intel’s Stratix 10 FPGA can reach the maximum operational frequency of 366 MHz. The 1-D MTS processor is able to process 44 fps@7680 × 4320 and greatly reduces the computational complexity of transformation in encoding and decoding.
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Working Draft 4 of Versatile Video Coding, document JVET M1001-v7, Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC (JTC 1/SC 29/WG 11) (2019)
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This study was funded by National Natural Science Foundation of China.
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Zhang, J., Shi, W. & Zhang, H. Study on versatile video coding multiple transform selection of hardware architecture based on FPGA. Multimed Tools Appl 82, 14929–14944 (2023). https://doi.org/10.1007/s11042-022-14069-3
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DOI: https://doi.org/10.1007/s11042-022-14069-3