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Performance-oriented FPGA-based convolution neural network designs

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Abstract

Convolutional neural network (CNN) is the most well-known algorithm that it has been widely utilized in the applications of the image recognition and classification. Various Field Programmable Gate Array based (FPGA-based) CNN architectures had been proposed for the capability of the fast reconfigurability. However, the high-performance designs are necessary to reduce the computational time. The contributions of the paper include: 1) using heterogeneous and two-dimensional dispatcher technologies to implement FPGA-based CNN accelerators at different computational levels of CNN so that the computational time of CNN can be reduced and 2) proposing a flexible and integrated pipeline software and hardware (SW/HW) architecture to reduce the integration overheads of using a CNN framework. The experimental results show that the proposed architectures have the best performance and minimum FPGA resource requirements.

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Funding

This work was supported by Ministry of Science and Technology, Taiwan, MOST 110–2221-E-024-001.

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  1. Department of Computer Science and Information Engineering, National University of Tainan, Tainan, Taiwan

    Chi-Chou Kao

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  1. Chi-Chou Kao
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Correspondence to Chi-Chou Kao.

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Kao, CC. Performance-oriented FPGA-based convolution neural network designs. Multimed Tools Appl 82, 21019–21030 (2023). https://doi.org/10.1007/s11042-023-14537-4

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