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Hardware architecture design for real-time SIFT extraction with reduced memory usage

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Abstract

Scale-invariant feature transform (SIFT) is considered one of the best algorithms to get feature points in an image. It maintains the accuracy in results even in image scaling, rotation, deformation, and light changes. However, memory requirements are the bottleneck to achieving real-time performance as SIFT has high computation complexity. Therefore, this paper has proposed the improved hardware architecture of the scale-invariant feature transform (SIFT) algorithm. The Gaussian pyramid is constructed using parallel operations instead of the original cascade operation to reduce memory requirements. Coordinate Rotation Digital Computer (CORDIC) has been adapted to perform trigonometric operations to reduce computational complexity. The ASIC design has been implemented using TSMC 90 nm technology. The system can achieve the performance of 35.6 FPS for an image resolution of 1280 × 720 while using only 237.4 Kbit of memory.

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Data availability

The datasets analyzed during the current study are available from the corresponding author on reasonable request.

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Funding

This work was supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 111–2221-E-008 -089 -MY3.

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Authors and Affiliations

  1. Department of Electronics Engineering, National Central University, Taoyuan, Taiwan

    Tsung-Han Tsai, Rui-Zhi Wang & Nai-Chieh Tung

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  1. Tsung-Han Tsai
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Correspondence to Tsung-Han Tsai.

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Tsai, TH., Wang, RZ. & Tung, NC. Hardware architecture design for real-time SIFT extraction with reduced memory usage. Multimed Tools Appl 83, 6297–6317 (2024). https://doi.org/10.1007/s11042-023-15789-w

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