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A routing algorithm for reducing optical loss in photonic Networks-on-Chip

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Abstract

Photonic Network-on-Chips is a new generation of Network-on-Chips and has been proposed as a novel solution for the communication infrastructure of chip multiprocessors as well as a different solution to eliminate limitations of Network-on-Chips. Photonic Network-on-Chips has important properties such as increasing communication bandwidth, lowering transmission latency, and lowering power consumption. These networks have some challenges such as routing for transfering photonic data over photonic layer. In this paper, we propose a new routing algorithm in which we use turning models, circuit-switching method, different traffic patterns such as Random, Paratec, Madbench, Bitreverse, Cactus, and Tornado to reduce optical loss to photonic layer. To do this, we have also considered non-blocking five-port router and 2-D Mesh topology. The new proposed routing algorithm can choose different source and destination nodes through selecting the path with the lowest optical loss. So to evaluate optical loss in different paths, we have considered best-case loss path, average-case, and worst-case. This was because we can use best-case loss path in order to transfer photonic data over photonic layer. In the end, proposed routing algorithm with turning models and different traffic patterns shows some improvements of optical loss in photonic layer and notably reduce this factor compared to the other XY dimension-order routing algorithm with 5 ports router.

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References

  1. Shacham, A., Bergmen, K., Carloni, L.P.: Photonic Network-on-Chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57, 1246–1260 (2008). doi:10.1109/TC.2008.78

    Article  MathSciNet  Google Scholar 

  2. Hung, M.K., Yaoyao, Y., Xiaowen, W., Wei, Z., Weichen, L., Jiang, X.: A hierarchical hybrid optical-electronic Network-on-Chip. In: Proceedings og IEEE Comput. SOC Ann. Symp. 327–332, (2010). doi:10.1109/ISVLSI.2010.17

  3. Miller, D.A.B.: Device requirements for optical interconnects to silicon chips. Proc. IEEE 977, 1166–1185 (2009). doi:10.1109/JPROC.2009.2014298

    Article  Google Scholar 

  4. Lee, B.G., Biberman, A., Chan, J., Bergmen, K.: High-performance modulators and switches for silicon photonic-Network-on-Chip. IEEE J. Sel. Topics Quantum Electron 16, 6–22 (2010). doi:10.1109/JSTQE.2009.2028437

    Article  Google Scholar 

  5. Min, R., Ji, R., Chen, Q., Zhang, L.: A universal method for constructing N-Port nonblocking optical router for photonic Networks-on-Chip. J. Lightwave Technol. 30, 3736–3741 (2012). doi:10.1109/JLT.2012.2227945

    Article  Google Scholar 

  6. Beausoleil, R.G., Kuekes, P.J., Snider, G.S., Yuan, W.S., Williams, R.S.: Nanoelectronic and nanophotonic interconnect. Proc. IEEE 96, 230–247 (2008). doi:10.1109/JPROC.2007.911057

    Article  Google Scholar 

  7. Xie, Y., Nikdast, M., Xu, J., Wu, X., Zhang, W., Ye, Y., Wang, X., Wang, Z., Liu, W.: Formal worst-case analysis of crosstalk noise in mesh-based optical Networks-on-Chip. IEEE Trans. Very large Scale integration (VLSI) Syst. 21, 1823–1836 (2012). doi:10.1109/TVLSI.2012.2220573

    Article  Google Scholar 

  8. Chan, J., Hendry, G., Bergman, K., Carloni, L.P.: Physical-layer modeling and system-level design of chip-scale photonic interconnection networks. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, 337–345 (2011). doi:10.1109/TCAD.2011.2157157

    Article  Google Scholar 

  9. Biberman, A., Preston, K., Hendry, G., Sherwood, N., Chan, J., Levy, J.S., Lipson, M., Bergman, K.: Photonic Network-on-Chip architectures using multilayer deposited silicon materials for high-performance chip multiprocessor. J. Emerge. Technol. Comput. Syst. 7, 1–25 (2011). doi:10.1145/1970406.1970409

    Article  Google Scholar 

  10. Pan, Y., Kumar, P., Kim, J., Memik, G., Zhang, Y., Choudhary, A.: Firefly: Illuminating future Network-on-Chip with nanophotonics. In: Presented at the Proceedings of the \(36^{{\rm th}}\) Annual International Symposium on Computer Architecture, Austin, Texas, USA, 429–440 (2009)

  11. Hatamirad, M., Reza, A., Shabani, H., Niazmand, B., Reshadi, M.: Loss-aware router design approach for dimension-ordered routing algorithms in Photonic Networks-on-Chip. IJCSI Int. J. Comput. Sci. Issues 9, 337–345 (2012)

    Google Scholar 

  12. Xie, Y., Nikdast, M., Xu, J., Zhang, W., Li, Q., Wu, X., Ye, Y., Wang, X., Liu, W.: Crosstalk noise and bit error rate analysis for optical Network-on-Chip. DAC’10 Anaheim California USA 657–660 (2010)

  13. Shacham, A., Hendry, G., Bergman, K., Carloni, L.P.: On the Design of a photonic Network-on-Chip. In: Networks-on-Chip first International Symposium 53–64 (2007)

  14. Gu, H., Hung, K.M., Xu, J., Zhang, W.: A Low-power low-cost optical router for optical Networks-on-Chip in multiprocessor System-on-Chip. In: IEEE Computer Society Annual Symposium on VLSI 19–24, (2009). doi:10.1109/ISVLSI.2009.19

  15. Ye, Y., Wu, X., Xu, J., Zhang, W., Nikdast, M., Wang, X.: Holistic comparison of optical routers for chip multiprocessors. supported by RPC11EG18 and SBI06/07. EG01-4 1–5. doi:10.1109/ICASID.2012.6325348 (2012)

  16. Gu, H., Xu, J., Wang, Z.: A novel optical mesh Network-on-Chip for gigascale Systems-on-chip. IEEE 1728–1731. (2008). doi:10.1109/APCCAS.2008.4746373

  17. Ji, R., Yang, L., Zhang, L., Tian, Y., Ding, J., Chen, H., Lu, Y., Zhou, P., Zhu, W.: Five-port optical router for photonic Networks-on-Chip. Opt. Expr. 19, 20258–202668 (2011). doi:10.1364/OE.19.020258

    Article  Google Scholar 

  18. Shacham, A., Lee, B.G., Chen, Q., Carloni, L.P.: Photonic NoC for DMA communications in chip multiprocessors. In: \(15^{{\rm th}}\) IEEE Symposium on High-performance Interconnects IEEE Computer Society, 29–38. doi:10.1109/HOTI.2007.9 (2007)

  19. Vantrease, D.: CORONA: System implications of emerging nanophotonic technology. In: Computer Architecture, ISCA ’08. \(35^{{\rm th}}\) International Symposium, 153–164. doi:10.1109/ISCA.2008.35 (2008)

  20. Joshi, A.: Silicon-photonic CLOS networks for Global on-Chips communication. In: Networks-on-Chip \(3^{{\rm RD}}\) ACM/IEEE International Symposium, 124–133. doi:10.1109/NOCS.2009.5071460 (2009)

  21. Koohi, S., Abdollahi, M., Hessabi, S.: All-optical wavelength-routed NoC based on a novel hierarchical topology. In: Networks-on-Chips (NoCs) Fifth IEEE/ACM International Symposium 97–104 (2011)

  22. Sherwood-Droz, N., Wang, H., Chen, L., Lee, B.G., Biberman, A., Bergman, K., Lipson, M.: Optical 4*4 hitless silicon router for Optical Networks-on-Chip (NoCs). Opt. Expr. 16, 15915–15922 (2008). doi:10.1364/OE.16.015915

    Article  Google Scholar 

  23. Hendry, G.: Time-division-multiplexed arbitration in silicon nanophotonic Networks-on-Chip for high performance chip multiprocessors. J. Parallel Distrib. Comput. 71, 641–650 (2011). doi:10.1016/j.jpdc.2010.09.009

    Article  Google Scholar 

  24. Wu Chan, J.: Architecture Exploration and Design Methodologies of Photonic Interconnection Networks. Columbia University, Columbia, New York City (2012)

    Google Scholar 

  25. Mo, K.H., Ye, Y., Wu, X., Zhang, W., Liu, W., Xu, J.: A Hierarchical hybrid optical-electronic Network-on-Chip. In: Presented at the proceedings of the 2010 IEEE Annual Symposium on VLSI (2010)

  26. Nikdast, M., Xu, J.: Crosstalk noise and loss analysis platform (CLAP) publishing Hong Kong University of Science and Technology. http://www.ece.ust.hk/~eexu/CLAP.html (2007)

  27. Chan, J., Hendry, G., Biberman, A., Bergman, K., Carloni, L.P.: Phoenixsim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks. In: Proceedings of the Conference on Design Automation and Test in Europe 691–696 (2010)

  28. Singh, A.: Load-balanced routing in interconnection networks. Submitted to the department of electrical engineering and the committee on graduate studies of Standford University in partial fulfillment of the requirements for the degree of Doctor of Philosophy (2005)

  29. Hendry, G., Kamil, S., Biberman, A., Chan, J., Lee, B.G., Mohiyuddin, M., Bergman, K., Carloni, L.P., Oliker, L., Shalf, J.: Analysis of photonic networks for a chip multiprocessor using scientific applications. In: 3rd ACM/IEEE International Symposium 104–113. doi:10.1109/NOCS.2009.5071458 (2009)

  30. Enright Jerger, N., Peh, L.S.: On-Chip Networks. A publication in the Morgan & Claypool publishers’ series synthesis lectures on computer architecture#8. doi:10.2200/S00209ED1V01Y200907CAC008 (2009)

  31. Chiu, G.M.: The odd-even turn model for adaptive routing. IEEE Trans. Parallel Distrib. Syst. 11(7), 729–738 (2000). doi:10.1109/71.877831

  32. Brown, J.W.: Adaptive Network on Chip routing using the turn model. B. S, University of New Hampshire in Partial Fulfillment of the requirement for Degree of Master of Science in Computer Science (2011)

  33. Mubeen, S., Kumar, S.: How to Design Source Routing for Mesh Topology Network on Chip?. Malardalen University, Sweden

  34. Hendry, G., Robinson, E., Gleyzer, V., Chan, J., Carloni, L.P., Bliss, N., Bergman, K.: Circuit-switched memory access in photonic interconnection networks for high-performance embedded computing. IEEE, New Orleans, Louisiana, USA 978-1- 4244-7558-2/10/$26.00 (2010)

  35. Bergmen, K., Carloni, L.P., Biberman, A., Chan, J., Hendry, G.: Photonic Network-on-Chip Design. Springer publishers, Integrated Circuit and Systems 68, (2014)

  36. Kachris, C., Tomkos, I.: A survey on optical interconnects for data centers, IEEE Commun. Surv. Tutor. vol. 14, No. 4, doi:10.1109/SURV.2011.122111.00069 (2012)

  37. Kachris, C., Bergman, K., Tomkos, I.: Optical Interconnects for Future Data Center Networks, Springer, New York, Heidelberg, Dordrecht, London, doi:10.1007/978-1-4614-4630-9

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Correspondence to Midia Reshadi.

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Asadi, B., Reshadi, M. & Khademzadeh, A. A routing algorithm for reducing optical loss in photonic Networks-on-Chip. Photon Netw Commun 34, 52–62 (2017). https://doi.org/10.1007/s11107-016-0656-x

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