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Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling

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Abstract

Reducing power consumption is quickly becoming a first-class optimization metric for many high-performance parallel computing platforms. One of the techniques employed by many prior proposals along this direction is voltage scaling and past research used it on different components such as networks, CPUs, and memories. In contrast to most of the existent efforts on voltage scaling that target a single component (CPU, network or memory components), this paper proposes and experimentally evaluates a voltage/frequency scaling algorithm that considers CPU and communication links in a mesh network at the same time. More specifically, it scales voltages/frequencies of CPUs in the nodes and the communication links among them in a coordinated fashion (instead of one after another) such that energy savings are maximized without impacting execution time. Our experiments with several tree-based sparse matrix computations reveal that the proposed integrated voltage scaling approach is very effective in practice and brings 13% and 17% energy savings over the pure CPU and pure communication link voltage scaling schemes, respectively. The results also show that our savings are consistent with the different network sizes and different sets of voltage/frequency levels.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, 16802, USA

    Seung Woo Son, Konrad Malkowski, Guilin Chen, Mahmut Kandemir & Padma Raghavan

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  1. Seung Woo Son
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  2. Konrad Malkowski
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  3. Guilin Chen
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  4. Mahmut Kandemir
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  5. Padma Raghavan
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Correspondence to Seung Woo Son.

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Son, S.W., Malkowski, K., Chen, G. et al. Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling. J Supercomput 41, 179–213 (2007). https://doi.org/10.1007/s11227-007-0113-9

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  • DOI: https://doi.org/10.1007/s11227-007-0113-9

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