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Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

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Abstract

This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore’s reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors.

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Authors and Affiliations

  1. School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, Fukushima-ken, Aizu-Wakamatsu-shi, 965-8580, Japan

    Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo & Kenichi Kuroda

  2. IBM Tokyo Research Laboratory, 1623-14 Shimotsuruma, Yamato-shi, Kanagawa-ken, 242-8502, Japan

    Arquimedes Canedo

Authors
  1. Ben Abdallah Abderazek
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  2. Masashi Masuda
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  3. Arquimedes Canedo
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  4. Kenichi Kuroda
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Correspondence to Ben Abdallah Abderazek.

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Abderazek, B.A., Masuda, M., Canedo, A. et al. Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture. J Supercomput 57, 314–338 (2011). https://doi.org/10.1007/s11227-010-0409-z

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