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The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs

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Abstract

This paper proposes two-dimensional directed graphs (or digraphs for short) as a promising alternative to the popular 2D mesh topology for networks-on-chip (NoCs). Mesh is the most popular topology for the NoCs, mainly due to its suitability for on-chip implementation and low cost. However, the fact that a digraph offers a lower diameter than its equivalent linear array of equal cost motivated us to evaluate digraphs as the underlying topology of NoCs. This paper introduces a family of NoC topologies based on three well-known digraphs, namely de Bruijn, shuffle-exchange, and Kautz. We study topological properties of the proposed topologies. We show that the proposed digraph-based topologies have several attractive features including constant node degree, low diameter and cost, and low zero load latency which result in superior performance over the mesh. We introduce a deadlock-free routing algorithm for the proposed NoC topologies and compare NoCs employing the proposed topologies and the mesh topology in terms of power consumption and performance. Simulation results also reveal that the proposed NoC topologies offer higher performance and consume lower power than the mesh NoC.

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References

  1. Benini L, Micheli GD (2002) Networks on chip: a new paradigm for systems on chip design. In: DATE02: design automation and test in Europe, pp 418–419

  2. Ogras UY, Hu J, Marculescu R (2005) Key research problems in NoC design: a holistic perspective. In: CODES+ISSS, Jersey City, NJ, pp 69–74

  3. Flores A, Aragon JL, Acacio ME (2008) An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J Supercomput 45(3):341–364

    Article  Google Scholar 

  4. Ogras UY, Marculescu R (2005) Application-specific network-on-chip architecture customization via long-range link insertion. In: ICCAD05: IEEE/ACM intl. conf. on computer aided design, pp 246–253

  5. Dally WJ (1991) Express cubes: improving the performance of K-ary N-cube interconnection networks. IEEE Trans Comput 40(9):1016–1023

    Article  Google Scholar 

  6. Kim J, Balfour J, Dally WJ (2007) Flattened butterfly topology for on-chip-networks. In: Micro07: 40th IEEE/ACM international symposium on microarchitecture, pp 172–182

  7. Grot B, Hestness J, Keckler SW, Mutlu O (2009) Express cube topologies for on-chip interconnects. In: HPCA09: 15th IEEE international symposium on high performance computer architectures, pp 163–174

  8. Sabbaghi-Nadooshan R, Modarressi M, Sarbazi-Azad H (2008) A novel high performance low power based mesh topology for NoCs. In: PMEO-2008, 7th international workshop on performance modeling, evaluation, and optimization, pp 1–7

  9. Sabbaghi-Nadooshan R, Modarressi M, Sarbazi-Azad H (2008) The 2d DBM: an attractive alternative to the mesh topology for network-on-chip. In: ICCD08: IEEE international conference on computer design, pp 486–490

  10. Sabbaghi-Nadooshan R, Sarbazi-Azad H (2008) The Kautz mesh: a new topology for SoCs. In: ISOCC08: international SoC design conference, pp 300–303

  11. Liu GP, Lee KY (1993) Optimal routing algorithms for generalized de Bruijn digraph. In: ICPP93: international conference on parallel processing, pp 167–174

  12. Stone H (1971) Parallel processing with perfect shuffle. IEEE Trans Comput 20(2):153–161

    Article  MATH  Google Scholar 

  13. Tan X, Sevcik KC (1986) Reduced distance routing in single-stage shuffle-exchange interconnection networks. Technical report, University of Toronto

  14. Sparso J et al (1991) An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures. IEEE J Solid-State Circuits 26(2):90–97

    Article  Google Scholar 

  15. De Bruijn NG (1946) A combinatorial problem. Proc K Ned Akad Wet 49(2):758–764

    Google Scholar 

  16. Samanathan MR, Pradhan DK (1989) The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI. IEEE Trans Comput. 38(4):567–581

    Article  MathSciNet  Google Scholar 

  17. Park H, Agrawal DP (1995) A novel deadlock-free routing technique for a class of de Bruijn based networks. In: IPPS, pp 524–531

  18. Ganesan E, Pradhan DK (2003) Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. In: ISCAS03: IEEE international symposium on circuits and systems, pp 870–873

  19. Louri A, Sung H (1995) An efficient 3D optical implementation of binary de Bruijn networks with applications to massively parallel computing. In: Second workshop on massively parallel processing using optical interconnections, pp 152–159

  20. Kautz WH (1969) The design of optimum interconnection networks for multiprocessors. In: Architecture and design of digital computers. Nato advanced summer institute, pp 249–277

  21. Imase M, Itoh M (1983) A design for directed graphs with minimum diameter. IEEE Trans Comput. 32(8):782–784

    Article  MATH  Google Scholar 

  22. Bermond JC, Dawas RW, Ergincan FO (1997) De Bruijn and Kautz bus networks. Networks 30(3):205–218

    Article  MathSciNet  MATH  Google Scholar 

  23. Park H, Agrawal DP (1995) Efficient deadlock-free wormhole routing in shuffle-based networks. In: Proc. 7th IEEE symposium on parallel and distributed processing, pp 92–99

  24. Dally WJ, Seitz C (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput 36(5):547–553

    Article  MATH  Google Scholar 

  25. Bopanna RV, Chalasani S (1996) A framework for designing deadlock-free wormhole routing algorithms. IEEE Trans Parallel Distrib Syst 7(2):169–183

    Article  Google Scholar 

  26. Duato J, Yalamanchili S, Li N (2005) Interconnection networks: an engineering approach. Morgan Kaufmann, San Mateo

    Google Scholar 

  27. Chen C, Agarwal P, Burke JR (1993) dBcube: a new class of hierarchical multiprocessor interconnection networks with area efficient layout. IEEE Trans Parallel Distrib Syst 4(12):1332–1344

    Article  Google Scholar 

  28. Parhami B (2002) Introduction to parallel processing. Kluwer Academic, Dordrecht

    Google Scholar 

  29. http://www.princeton.edu/~lshang/popnet.html, August 2007

  30. Wang H, Zhu X, Peh L-S, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Micro02: 35th international symposium on microarchitecture, pp 294–305

  31. Mullins R, West A, Moore S (2006) The design and implementation of a low-latency on-chip network. In: ASPDAC06: Asia and South Pacific design automation conference, pp 164–169

  32. Kahng A, Li B, Peh L-S, Samadi K (2009) Orion2.0: a fast and accurate NoC power and area model for early-stage design space exploration. In: DATE09, pp 423–428

  33. Goossens K, Dielissen J, Radulescu A (2005) Æthe real network on chip: concepts, architectures and implementations. IEEE Des Test Comput 22(5):414–421

    Article  Google Scholar 

  34. Owens J, Dally WJ, Ho R, Jayasimha DN, Keckler SW, Peh L-S (2007) Research challenges for on-chip interconnection networks. IEEE Micro 27(5):96–108

    Article  Google Scholar 

  35. Bhandarkar SM, Arabnia HR, Smith JW (1995) A reconfigurable architecture for image processing and computer vision. Int J Pattern Recogn Artif Intell 9:201–229

    Article  Google Scholar 

  36. Bhandarkar SM, Arabnia HR (1995) The Hough transform on a reconfigurable multi-ring network. J Parallel Distrib Comput 24:107–114

    Article  Google Scholar 

  37. Arif Wani M, Arabnia HR (2003) Parallel edge-region-based segmentation algorithm targeted at reconfigurable multi-ring network. J Supercomput 25:43–63

    Article  MATH  Google Scholar 

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Correspondence to Hamid Sarbazi-Azad.

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Sabbaghi-Nadooshan, R., Modarressi, M. & Sarbazi-Azad, H. The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs. J Supercomput 59, 1–21 (2012). https://doi.org/10.1007/s11227-010-0410-6

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  • DOI: https://doi.org/10.1007/s11227-010-0410-6

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