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Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization

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Abstract

Encapsulating critical computation subgraphs as application-specific instruction set extensions is an effective technique to enhance the performance and energy efficiency of embedded processors. However, the addition of custom functional units to the base processor is required to support the execution of custom instructions. Although automated tools have been developed to reduce the long design time needed to produce a new extensible processor for each application, short time-to-market, significant non-recurring engineering and design costs are issues. To address these concerns, we introduce an adaptive extensible processor in which custom instructions are generated and added after chip-fabrication. To support this feature, custom functional units (CFUs) are replaced by a reconfigurable functional unit (RFU). The proposed RFU is based on a matrix of functional units which is multi-cycle with the capability of conditional execution. To generate more effective custom instructions, they are extended over basic blocks and hence, multiple-exits custom instruction and intuition behind it are introduced. Conditional execution capability has been added to the RFU to support the multi-exit feature of custom instructions. Because the proposed RFU has limitations on hardware resources (i.e., connections and processing elements), an integrated mapping-temporal partitioning framework is proposed to guarantee that the generated custom instructions can be mapped on the RFU (mappable custom instructions). Experimental results show that multi-exit custom instructions enhance the performance and energy efficiency by an average of 32% and 3% compared to custom instructions limited to one basic block, respectively. A maximum speedup of 4.9, compared to a single-issue embedded processor, and an average speedup of 1.9 was achieved on MiBench benchmark suite. The maximum and average energy saving are 56% and 22%, respectively. These performance and energy efficiency are obtained at the cost of 30% area overhead.

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Author information

Authors and Affiliations

  1. School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

    Hamid Noori

  2. E-JUST Center, Kyushu University, Fukuoka, Japan

    Farhad Mehdipour

  3. Department of Advanced Information Technology, Kyushu University, Fukuoka, Japan

    Koji Inoue & Kazuaki Murakami

Authors
  1. Hamid Noori
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  2. Farhad Mehdipour
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  3. Koji Inoue
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  4. Kazuaki Murakami
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Corresponding author

Correspondence to Hamid Noori.

Additional information

A first version of this work appeared in Design Automation and Test in Europe (DATE), 2007 under the title “Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor” and International Symposium on Low Power Electronics and Design (ISLPED), 2008 under the title “Enhancing Energy Efficiency of Processor-Based Embedded Systems through Post-Fabrication ISA Extension”.

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Noori, H., Mehdipour, F., Inoue, K. et al. Improving performance and energy efficiency of embedded processors via post-fabrication instruction set customization. J Supercomput 60, 196–222 (2012). https://doi.org/10.1007/s11227-010-0505-0

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  • DOI: https://doi.org/10.1007/s11227-010-0505-0

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