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Active memory controller

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Abstract

Inability to hide main memory latency has been increasingly limiting the performance of modern processors. The problem is worse in large-scale shared memory systems, where remote memory latencies are hundreds, and soon thousands, of processor cycles. To mitigate this problem, we propose an intelligent memory and cache coherence controller (AMC) that can execute Active Memory Operations (AMOs). AMOs are select operations sent to and executed on the home memory controller of data. AMOs can eliminate a significant number of coherence messages, minimize intranode and internode memory traffic, and create opportunities for parallelism. Our implementation of AMOs is cache-coherent and requires no changes to the processor core or DRAM chips.

In this paper, we present the microarchitecture design of AMC, and the programming model of AMOs. We compare AMOs’ performance to that of several other memory architectures on a variety of scientific and commercial benchmarks. Through simulation, we show that AMOs offer dramatic performance improvements for an important set of data-intensive operations, e.g., up to 50× faster barriers, 12× faster spinlocks, 8.5×–15× faster stream/array operations, and 3× faster database queries. We also present an analytical model that can predict the performance benefits of using AMOs with decent accuracy. The silicon cost required to support AMOs is less than 1% of the die area of a typical high performance processor, based on a standard cell implementation.

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Authors and Affiliations

  1. nVidia Corporation, Santa Clara, USA

    Zhen Fang & Michael A. Parker

  2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Lixin Zhang

  3. IBM Austin Research Lab, Austin, USA

    John B. Carter

  4. Chalmers University of Technology, Gothenburg, Sweden

    Sally A. McKee

  5. AMD, Sunnyvale, USA

    Ali Ibrahim

  6. Intel Labs, Intel Corporation, Santa Clara, USA

    Xiaowei Jiang

Authors
  1. Zhen Fang
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Correspondence to Zhen Fang.

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The work was done when most of the authors were at the University of Utah. The views and conclusions contained herein are those of the authors and should not be interpreted as representing those, either express or implied, of Intel, CAS, IBM, Chalmers, AMD, nVidia, or the University of Utah.

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Fang, Z., Zhang, L., Carter, J.B. et al. Active memory controller. J Supercomput 62, 510–549 (2012). https://doi.org/10.1007/s11227-011-0735-9

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