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TM: a new and simple topology for interconnection networks

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Abstract

The selection of a topology is essential to the performance of interconnection networks, so designing a new, cost-effective topology is very significant. 2D mesh is one of the most popular topologies. However, the diameter and average distance of a 2D mesh are large enough to greatly influence the performance of the network. This paper presents a novel topology called TM, which combines the advantages of both a 2D torus and a 2D mesh. For an n×n network, the total number of links in a TM is the same as that in a mesh, while the diameter of a TM is extremely close to that of a torus. Besides, the average distance of a TM is at the middle of that of a torus and that of a mesh. To prevent deadlocks in TMs, a virtual network partitioning scheme is adopted into the TM network. Moreover, both of the deterministic and fully-adaptive routing techniques in TMs are proposed in this paper. Compared to mesh, the TM network provides average distance and diameter reduction, which contributes to the performance enhancement. Sufficient simulation results are presented to show the effectiveness of the TM network, and the new routing schemes proposed for it, by comparing with the mesh network. Compared to the torus, which requires at least 3 virtual channels to support fully-adaptive routing, the TM network can support fully-adaptive routing with only 2 virtual channels. Seen from the experimental results, in most cases, the performance of TM is worse than the torus, while in some cases, the performance of TM is comparable to torus or even better than the torus.

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Notes

  1. Here, we assume that each node in the network devotes w pins to communicate with a neighbor along the X (or Y) dimension.

References

  1. Flich J, Bertozzi D (2011) Designing network-on-chip architectures in the nanoscale era. Chapman and Hall/CRC, London/New York

    Google Scholar 

  2. Xu Y, Zhao B, Zhou X, Zhang Y, Yang J (2009) A low-radix and low-diameter 3D interconnection network design. In: Proceedings of international symposium on high performance computer architecture, Oct 2009, pp 30–42

    Google Scholar 

  3. Duato J, Yalamanchili S, Ni L (1997) Interconnection networks: an engineering approach. IEEE Press, New York

    Google Scholar 

  4. Samatham MR, Pradhan DK (1989) The de Bruijn multiprocessor network: a versatile parallel processing and sorting network for VLSI. IEEE Trans Comput 38(4):567–581

    Article  MathSciNet  MATH  Google Scholar 

  5. Hsieh SY, Hsiao TT (2006) The k-degree Cayley graph and its topological properties. Networks 47(1):26–36

    Article  MathSciNet  MATH  Google Scholar 

  6. Chen Y, Hu J, Ling X, Huang T (2012) A novel 3D NoC architecture based on De Bruijn graph. J Comput Electr Eng 38(3):801–810

    Article  Google Scholar 

  7. Scott SL, Thorson GM (1996) The Cray T3E network: adaptive routing in a high performance 3D torus. In: Proceedings of international symposium on high-performance interconnects, hot interconnects IV

    Google Scholar 

  8. Dally WJ, Towles B (2004) Principles and practices of interconnection networks. Morgan Kaufmann, San Francisco

    Google Scholar 

  9. Allen FE et al (2001) Blue gene: a vision for protein science using a petaflop supercomputer. IBM Syst J 40(2):310–327

    Article  Google Scholar 

  10. Adiga NR, Blumrich MA et al (2005) Blue gene/L torus interconnection network. IBM J Res Dev 49(2):265–276

    Article  Google Scholar 

  11. Brightwell R, Pedretti KT, Underwood KD, Hudson T (2006) Seastar interconnect: balanced bandwidth for scalable performance. IEEE MICRO 26(3):41–57

    Article  Google Scholar 

  12. Feero BS, Pande PP (2009) Networks-on chip in a three-dimensional environment: a performance evaluation. IEEE Trans Comput 58(1):32–45

    Article  MathSciNet  Google Scholar 

  13. Grot B, Keckler SW (2008) Scalable on-chip interconnect topologies. In: Proceedings of international workshop on chip multiprocessor memory systems and interconnects, in conjunction with international symposium on computer architecture, Jun 2008

    Google Scholar 

  14. Wang J, Li Y, Li H (2012) A performance analytical strategy for network-on-chip router with input buffer architecture. Adv Electr Comput Eng 12(4):19–24

    Article  Google Scholar 

  15. Shin M, Kim J (2011) Leveraging torus topology with deadlock recovery for cost-efficient on-chip network. In: Proceedings of IEEE international conference on computer design, Oct 2011, pp 25–30

    Google Scholar 

  16. Xiang D, Zhang Y, Sun J (2008) Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes. J Syst Archit 54(12):1164–1178

    Article  Google Scholar 

  17. Kim J, Nicopoulos C, Park D, Das R, Xie Y, Narayanan V, Yousif MS, Das C (2007) A novel dimensionally-decomposed router for on-chip communication in 3D architecture. In: Proceedings of the 34th international symposium on computer architecture, pp 4–15

    Google Scholar 

  18. Linder DH, Harden JC (1991) An adaptive and fault tolerant wormhole routing strategy for k-ary n-cubes. IEEE Trans Comput 40(1):2–12

    Article  MathSciNet  Google Scholar 

  19. Xiang D (2011) Deadlock-free adaptive routing in meshes with fault-tolerance ability using channel overlapping. IEEE Trans Dependable Secure Comput Jan:74–88

    Article  Google Scholar 

  20. Luo W, Xiang D (2012) An efficient deadlock-free adaptive routing algorithm for torus networks. IEEE Trans Parallel Distrib Syst 23(5):800–808

    Article  Google Scholar 

  21. Amine JA, Aimen B, Frederic P (2006) Programming models and HW-SW interfaces abstraction for multi-processor. In: Proceedings of the 43rd design automation conference, pp 280–285

    Google Scholar 

  22. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the design automation conference, Jun 2001

    Google Scholar 

  23. Xiang D, Zhang Y, Pan Y (2009) Practical deadlock-free fault-tolerant routing in meshes based on the planar network fault model. IEEE Trans Comput 58(5):620–633

    Article  MathSciNet  Google Scholar 

  24. Xiang D, Zhang Y (2011) Cost-effective power-aware core testing in NoCs based on a new unicast-based multicast scheme. IEEE Trans Comput-Aided Des Integr Circuits Syst 30(1):135–147

    Article  MathSciNet  Google Scholar 

  25. Ascia G, Catania V, Palesi M, Patti D (2008) Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans Comput 57(6):809–820

    Article  MathSciNet  Google Scholar 

  26. Singh A, Dally WJ, Gupta AK, Towles B (2003) GOAL: a load-balanced adaptive routing algorithm for torus networks. In: Proceedings of the international symposium on computer architecture, May 2003

    Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China

    Xinyu Wang & Zhigang Yu

  2. School of Software, Tsinghua University, Beijing, 100084, China

    Dong Xiang

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  1. Xinyu Wang
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  2. Dong Xiang
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  3. Zhigang Yu
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Correspondence to Xinyu Wang.

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Wang, X., Xiang, D. & Yu, Z. TM: a new and simple topology for interconnection networks. J Supercomput 66, 514–538 (2013). https://doi.org/10.1007/s11227-013-0922-y

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