Skip to main content

Advertisement

Springer Nature Link
Log in

Modeling computational limitations in H-Phy and Overlay-NoC architectures

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

High performance computing demands constant growth in computational power and services that can be offered by modern supercomputers. It requires technological and designing advances in the multiprocessor internal structures as well as novel computing models considering the very high computing demands. One of the increasingly important requirements of computing platforms is a functionality that allows efficient managing computational resources, i.e., monitor them, restrict an access to some part of the resources, account for computational service, or ensure reliability and quality of service when some resources are broken or disabled. In this paper, we present a new model describing computational limitations for processing tasks on multiprocessor systems. The model is implemented in Hardware-Physical (H-Phy) and Overlay-Network-on-Chip (Overlay-NoC) architectures. Both architectures and the model are described and analyzed. Experimentation system is also presented, together with simulation assumptions, results of research and their study. The paper provides complete models of H-Phy and Overlay-NoC structures with an ability to restrict processing resources.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. Andersson B (2010) Assigning real-time tasks on heterogeneous multiprocessors with two unrelated types of processors. In: Real-time systems symposium (RTSS), pp 239–248. doi:10.1109/RTSS.2010.32

    Google Scholar 

  2. Antunes E et al (2012) Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC. In: 13th international symposium on quality electronic design (ISQED), pp 451–457. doi:10.1109/ISQED.2012.6187532

    Chapter  Google Scholar 

  3. Bowman KA, Alameldeen AR, Srinivasan ST, Wilkerson CB (2007) Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. In: Proceedings of the 2007 international symposium on low power electronics and design (ISLPED ’07), pp 50–55. doi:10.1145/1283780.1283792

    Chapter  Google Scholar 

  4. Chmaj G, Walkowiak K (2012) Decision strategies for a P2P computing system. J Univers Comput Sci 18(5):599–622

    Google Scholar 

  5. Chmaj G, Zydek D, Elhalwagy YZ, Selvaraj H (2012) Overlay-NoC and H-Phy based computing using modern chip multiprocessors. In: Proceedings of 2012 IEEE international conference on electro/information technology (EIT 2012). IEEE Computer Society, Los Alamitos, pp 1–6. doi:10.1109/EIT.2012.6220604

    Chapter  Google Scholar 

  6. Daoud LB, Ragab ME, Goulart V (2011) Faster processor allocation algorithms for mesh-connected CMPs. In: Proceedings of 14th euromicro conference on digital system design (DSD 2011), pp 805–808. doi:10.1109/DSD.2011.107

    Chapter  Google Scholar 

  7. De Giusti L, Chichizola F, Naiouf M, De Giusti A (2008) Mapping tasks to processors in heterogeneous multiprocessor architectures: the MATEHa algorithm. In: International conference of the Chilean computer science society, pp 85–91. doi:10.1109/SCCC.2008.11

    Google Scholar 

  8. Enokido T, Aikebaier A, Takizawa M (2011) Process allocation algorithms for saving power consumption in peer-to-peer systems. IEEE Trans Ind Electron 58(6):2097–2105. doi:10.1109/TIE.2010.2060453

    Article  Google Scholar 

  9. Feichtinger C, Donath S, Köstler H, Götz J, Rüde U (2011) WaLBerla: HPC software design for computational engineering simulations. J Comput Sci 2(2):105–112. doi:10.1016/j.jocs.2011.01.004

    Article  Google Scholar 

  10. Hendrya G et al (2011) Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors. J Parallel Distrib Comput 71(5):641–650. doi:10.1016/j.jpdc.2010.09.009

    Article  Google Scholar 

  11. Intel Microprocessor Export Compliance Metrics (2011) http://download.intel.com/support/processors/corei5/sb/core_i5-600_d.pdf

  12. Jayasimh DN, Zafar B, Hoskote Y (2006) On-chip Interconnection Networks: Why They Are Different and How to Compare Them. Intel

  13. Jensen D, Rodrigues A (2010) Embedded systems and exascale computing. Comput Sci Eng 12(6):20–29. doi:10.1109/MCSE.2010.95

    Article  Google Scholar 

  14. Law AM (2009) How to build valid and credible simulation models. In: Proceedings of the 2009 winter simulation conference (WSC), pp 24–33. doi:10.1109/WSC.2009.5429312

    Chapter  Google Scholar 

  15. Lee Y, Zomaya A (2011) Energy conscious scheduling for distributed computing systems under different operating conditions. IEEE Trans Parallel Distrib Syst 22(6):1374–1381. doi:10.1109/TPDS.2010.208

    Article  Google Scholar 

  16. Lin Y, Chen W, Su A, Chang D (2011) A low cost, low power, high scalability and dependability processor-cluster platform. In: 6th IEEE international symposium on industrial embedded systems (SIES), pp 95–98. doi:10.1109/SIES.2011.5953689

    Google Scholar 

  17. Nadeem MF, Ostadzadeh SA, Wong S, Bertels K (2011) Task scheduling strategies for dynamic reconfigurable processors in distributed systems. In: Proceedings on international conference on high performance computing and simulation (HPCS), pp 90–97. doi:10.1109/HPCSim.2011.5999811

    Google Scholar 

  18. Satish N et al (2010) Fast sort on CPUs, GPUs and Intel MIC architectures. Technical Report, Intel

  19. Shen H, Qiu Q (2011) An FPGA-based distributed computing system with power and thermal management capabilities. In: Proceedings of 20th international conference on computer communications and networks (ICCCN), pp 1–6. doi:10.1109/ICCCN.2011.6005802

    Google Scholar 

  20. Schranzhofer A, Chen J, Thiele L (2010) Dynamic power-aware mapping of applications onto heterogeneous MPSoC platforms. IEEE Trans Ind Inform 6(4):692–707. doi:10.1109/TII.2010.2062192

    Article  Google Scholar 

  21. Voigt A, Witkowski T (2012) A multi-mesh finite element method for Lagrange elements of arbitrary degree. J Comput Sci 3(5):420–428. doi:10.1016/j.jocs.2012.06.004

    Article  Google Scholar 

  22. Chmaj G, Walkowiak K, Tarnawski M, Kucharzak M (2012) Heuristic algorithms for optimization of task allocation and result distribution in peer-to-peer computing systems. Int J Appl Math Comput Sci 22(3):733–748. doi:10.2478/v10006-012-0055-0

    MathSciNet  Google Scholar 

  23. Zydek D, Selvaraj H (2011) Fast and efficient processor allocation algorithm for torus-based chip multiprocessors. J Comput Electr Eng 37(1):91–105. doi:10.1016/j.compeleceng.2010.10.001

    Article  MATH  Google Scholar 

  24. Zydek D, Selvaraj H (2010) Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors. J Microprocess Microsystems 34(1):39–48. doi:10.1016/j.micpro.2009.11.003

    Article  Google Scholar 

  25. Zydek D, Selvaraj H, Borowik G, Luba T (2011) Energy characteristic of processor allocator and network-on-chip. Int J Appl Math Comput Sci 21(2):385–399. doi:10.2478/v10006-011-0029-7

    Article  Google Scholar 

  26. Zydek D, Selvaraj H, Koszalka L, Pozniak-Koszalka I (2010) Evaluation scheme for NoC-based CMP with integrated processor management system. Int J Electron Telecommun 56(2):157–168. doi:10.2478/v10177-010-0021-4

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Idaho State University, Pocatello, USA

    Dawid Zydek & Steve Chiu

  2. Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA

    Grzegorz Chmaj

Authors
  1. Dawid Zydek
    View author publications

    You can also search for this author inPubMed Google Scholar

  2. Grzegorz Chmaj
    View author publications

    You can also search for this author inPubMed Google Scholar

  3. Steve Chiu
    View author publications

    You can also search for this author inPubMed Google Scholar

Corresponding author

Correspondence to Dawid Zydek.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zydek, D., Chmaj, G. & Chiu, S. Modeling computational limitations in H-Phy and Overlay-NoC architectures. J Supercomput 70, 301–320 (2014). https://doi.org/10.1007/s11227-013-0932-9

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-013-0932-9

Keywords