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Random data-aware flash translation layer for NAND flash-based smart devices

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Abstract

The design of flash memory systems for smart devices differs significantly from traditional storage systems, because most updates involve the random data. A previously proposed algorithm known as Switchable Address Translation (SAT) enhances the performance of multimedia storage devices; however, it exhibits low space utilization and executes intense monitoring. In this paper, we propose the Random Data-Aware Flash Translation Layer (RDA), which enhances the performance and durability of smart devices. RDA improves low space utilization using the state transition. Furthermore, RDA prolongs the durability of the flash memory by spreading out the random data. According to our experiment results, RDA reduces the total number of erase operations and narrows the deviation of erase operations between the physical blocks, when compared to SAT.

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Acknowledgements

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2012R1A1A2043422 and NRF-2013R1A1A2A10012956).

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Authors and Affiliations

  1. Department of Computer Engineering, Ajou University, Suwon, South Korea

    Se Jin Kwon

  2. Department of Information & Computer Engineering, Ajou University, Suwon, South Korea

    Hyung-Ju Cho, Sungsoo Kim & Tae-Sun Chung

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  1. Se Jin Kwon
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  2. Hyung-Ju Cho
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  4. Tae-Sun Chung
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Correspondence to Se Jin Kwon.

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Kwon, S.J., Cho, HJ., Kim, S. et al. Random data-aware flash translation layer for NAND flash-based smart devices. J Supercomput 66, 81–93 (2013). https://doi.org/10.1007/s11227-013-0979-7

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  • DOI: https://doi.org/10.1007/s11227-013-0979-7

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