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Formalization and configuration methodology for high-radix combined switches

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Abstract

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency since hop count is also reduced. However, there are some difficulties related to integration scale to design such switches. In this paper we present and formalize an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller switches to obtain switches having greater number of ports. This strategy will remain valid as the scale of integration keeps evolving. Although simple, this strategy raises key design challenges in order to these high-radix switches achieve the best performance. The resultant internal structure of these switches becomes an important design decision, and an arbitrary selection may produce a significant performance degradation. For this reason, we also propose a general methodology to configure in an optimal way the internal switch structure and apply it to a particular case in order to show how it works. The resultant switch configurations are evaluated in order to show the real potential of our proposal.

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Notes

  1. We distinguish between network-level connection pattern and switch-level connection pattern. The former is the traditional interconnection pattern connecting switch-based networks (e.g., butterfly permutation in multistage interconnection networks); the latter refers to how the ports of this kind of high-radix switches are mapped to the ports of the internal switches.

  2. In what follows, we will also use “internal link” to refer to the ports in \(\mathcal {J}\) that interconnect \(\alpha \) and \(\beta \) switches.

References

  1. Abts D, Marty M, Wells PM, Klausler P, Liu H (2010) Energy proportional datacenter networks. In: Proceedings of the 37th annual international symposium on computer architecture, ACM, New York, NY, USA, pp 338–347

  2. Binkert N, Davis A, Jouppi NP, McLaren M, Muralimanohar N, Schreiber R, Ahn JH (2011) The role of optics in future high radix switch design. In: Proceedings of the 38th annual international symposium on computer architecture, ACM, New York, NY, USA, pp 437–448

  3. Dally W, Towles B (2003) Principles and practices of interconnection networks. Morgan Kaufmann Publishers Inc, San Francisco, CA, USA

  4. Dally W, Hanrahan P, Erez M, Knight T, Labonte F, Ahn JH, Jayasena N, Kapasi U, Das A, Gummaraju J, Buck I (2003) Merrimac: supercomputing with streams. In: Proceedings of the 2003 ACM/IEEE conference on supercomputing, ACM, Phoenix, AZ, USA, p 35

  5. Dongarra JJ (2013) Report of the visit to the National University for Defense Technology Changsha, China

  6. Dongarra JJ, Meuer HW, Strohmaier E (2010) TOP500 Supercomputer sites. www.top500.org

  7. Duato J, Yalamanchili S, Ni L (2003) Interconnection networks: an engineering approach. Morgan Kaufmann Publishers Inc, San Francisco, CA, USA

  8. Eberle H, Garcia PJ, Flich J, Duato J, Drost R, Gura N, Hopkins D, Olesinski W (2008) High-radix crossbar switches enabled by proximity communication. In: Proceedings of the 2008 ACM/IEEE conference on supercomputing. IEEE Press, Austin, TX, USA, pp 1–12

  9. Gómez C, Gilabert F, Gómez ME, López P, Duato J (2007) Deterministic versus adaptive routing in fat-trees. In: Proceedings of workshop on communication architecture for clusters. IEEE Press, Los Alamitos, CA, USA, pp 1–8

  10. Gusat M, Abel F, Gramsamer F, Luijten R, Minkenberg C, Verhappen M (2003) Stability degree of switches with finite buffers and non-negligible round-trip time. Int Conf Comput Commun Netw 27(5):243–252

    Google Scholar 

  11. IBA (2007) InfiniBand architecture specification, vol 1, release 1.2.1

  12. ITRS (2010) International technology roadmap for semiconductors: 2010 update. www.itrs.net/Links/2010ITRS/Home2010.htm

  13. Kim J, Dally WJ, Towles B, Gupta AK (2005) Microarchitecture of a high-radix router. SIGARCH Comput Archit News 33(2):420–431

    Article  Google Scholar 

  14. Kim J, Dally WJ, Scott S, Abts D (2008) Technology-driven, highly-scalable Dragonfly topology. In: Proceedings of the 35th annual international symposium on computer architecture, IEEE Computer Society, Washington, DC, USA, pp 77–88

  15. Leighton F (1992) Introduction to parallel algorithms and architectures: arrays, trees, hypercubes. Morgan Kaufmann Publishers Inc, San Francisco, CA, USA

  16. Minkenberg C, Gusat M (2007) Speculative flow control for high-radix datacenter interconnect routers. In: Proceedings of the parallel and distributed processing symposium, IEEE Computer Society, Los Alamitos, CA, USA 1–10

  17. Minkenberg C, Abel F, Muller P, Krishnamurthy R, Gusat M, Hemenway BR (2005) Control path implementation for a low-latency optical HPC switch. In: Proceedings of the 13th symposium on high performance interconnects, IEEE Computer Society, Washington, DC, USA, pp 29–35

  18. Mora G, Flich J, Duato J, López P, Baydal E, Lysne O (2006) Towards an efficient switch architecture for high-radix switches. In: Proceedings of the 2006 ACM/IEEE symposium on architecture for networking and communications systems, ACM, New York, NY, USA, pp 11–20

  19. Oracle (2010) Sun Datacenter Infiniband Switch 36, Sun Datacenter Infiniband Switch 72, Sun Datacenter Infiniband Switch 648: architecture and deployment. White Paper, April, 2010. http://www.oracle.com/us/sun/sun-datacenter-ib-switches-arch-wp-071733.pdf

  20. Petrini F, Vanneschi M (1995) K-ary n-trees: high performance networks for massively parallel architectures, technical report, TR-95-18, University of Pisa

  21. Reinemo SA, Sem-Jacobsen FO, Skeie T (2012) Fat-trees and Dragonflies: a perspective on topologies. Contributed talk at the HPC Advisory Council Workshop, Lugano, Switzerland

  22. Scott S, Abts D, Kim J, Dally WJ (2006) The BlackWidow high-radix Clos network. SIGARCH Comput Archit News 34(2):16–28

    Article  Google Scholar 

  23. Villar JA, Andújar FJ, Alfaro FJ, Sánchez JL, Duato J (2011) An alternative for building high-radix switches: formalization and configuration methodology. Technical Report DIAB-11-02-1, Department of Computing Systems. University of Castilla-La Mancha. www.dsi.uclm.es/descargas/technicalreports/DIAB-11-02-1/diab-11-02-1

  24. Villar JA, Andújar FJ, Sánchez JL, Alfaro FJ, Duato J (2011) Evaluation of an alternative for increasing switch radix. In: Proceedings of the 10th IEEE international symposium on network computing and applications (NCA), IEEE Computer Society, Washington, DC, USA

  25. Villar JA, Andújar FJ, Sánchez JL, Alfaro FJ, Gámez JA, Duato J (2013) Obtaining the optimal configuration of high-radix combined switches. J Parallel Distrib Comput 73(9):1239–1250

    Article  Google Scholar 

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Acknowledgments

This work has been supported by the Spanish MINECO under grant TIN2012-38341-C04, and the Spanish MICINN under grant AP2010-4680.

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Authors and Affiliations

  1. Computing Systems Department, University of Castilla-La Mancha, Campus Universitario s/n, P.O. Box 02071, Albacete, Spain

    Juan A. Villar, Francisco J. Andújar, Francisco J. Alfaro & José L. Sánchez

  2. Department of Systems Data Processing and Computers, Technical University of Valencia, Camino de Vera s/n, P.O. Box 46022, Valencia, Spain

    José Duato

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  1. Juan A. Villar
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  2. Francisco J. Andújar
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  3. Francisco J. Alfaro
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  4. José L. Sánchez
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  5. José Duato
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Correspondence to Juan A. Villar.

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Villar, J.A., Andújar, F.J., Alfaro, F.J. et al. Formalization and configuration methodology for high-radix combined switches. J Supercomput 69, 1410–1444 (2014). https://doi.org/10.1007/s11227-014-1223-9

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