Skip to main content
Log in

An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

The chip multiprocessor is the most prolific processor design because its many cores enhance system performance. Network on chip (NOC) has been proposed as a promising model to solve the connection problem of the cores. However, a new challenge consists of fully benefiting from the on-chip network and the cores. In this paper, we propose a novel energy-efficient design of a microkernel-based on-chip operating system for an NOC-based manycore system. The operating system (OS) is partitioned into the microkernel and the other OS modules. They are distributed on the network to provide services to the user programs. Our experimental results show that our design can improve system performance with reduced power consumption.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

References

  1. Peh LS, Dally WJ (2001) A delay model and speculative architecture for pipelined routers. In: Proc. Seventh International Symposium on High-Performance Computer Architecture, pp 255–266. doi:10.1109/HPCA.2001.903268

  2. Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Comput Surv 38(1). doi:10.1145/1132952.1132953 (article no. 1)

  3. Ho R, Mai K, Horowitz M (2001) The future of wires. Proc IEEE 89(4):490–504. doi:10.1109/5.920580

    Article  Google Scholar 

  4. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proc. annual Design. Automation Conference, pp 684–689. doi:10.1145/378239.379048

  5. Wai HH, Pinkston TM (2003) A methodology for designing efficient on-chip interconnects on well-behaved communication patterns. In: Proc. Ninth International Symposium on High-Performance Computer. Architecture, pp 377–388. doi:10.1109/HPCA.2003.1183554

  6. Srinivasan K, Chatha KS (2005) ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis. In: Proc. 18th International Conference on VLSI Design, pp 623–628. doi:10.1109/ICVD.2005.113

  7. Murali S, Benini L, De Micheli G (2005) Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. In: Proc. Conference on 2005 Asia and South Pacific Design Automation, vol 1, pp 27–32. doi:10.1109/ASPDAC.2005.1466124

  8. Ascia G, Catania V, Palesi M (2004) Multi-objective mapping for mesh-based NoC architectures. In: Proc. 2004 International Conference on Hardware/Software Codesign and System Synthesis, pp 182–187. doi:10.1109/CODES+ISSS.2004.42

  9. Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. In: Proc. 2004 Conference on Design, Automation and Test in Europe, vol 2, pp 896–901. doi:10.1109/DATE.2004.1269002

  10. Marcon C, Calazans N, Moraes F et al (2005) Exploring NoC mapping strategies: an energy and timing aware technique. In: Proc. 2005 Conference on Design, Automation and Test in Europe, vol 1, pp 502–507. doi:10.1109/DATE.2005.149

  11. Barcelos D, Brião EW, Wagner FR (2007) A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. In: Proc. 20th annual Conference on Integrated Circuits and Systems Design, pp 282–287. doi:10.1145/1284480.1284557

  12. Hu J, Marculescu R (2004) Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: Proc. Conference on Design, automation and test in Europe, vol 1, pp 234–239. doi:10.1109/DATE.2004.1268854

  13. Brião EW, Barcelos D, Wronski F, Wagner FR (2007) Impact of task migration in NoC-based MPSoCs for soft real-time applications. In: Proc. IFIP International Conference on Very Large Scale Integration, pp 296–299. doi:10.1109/VLSISOC.2007.4402516

  14. Orozco D, Garcia E, Khan R et al (2012) Toward high-throughput algorithms on many-core architectures. ACM Trans Archit Code Optim 8(4). doi:10.1145/2086696.2086728 (article no. 49)

  15. Singh AK, Kumar A, Srikanthan T (2011) A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. In: Proc. 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, pp 175–184. doi:10.1145/2038698.2038726

  16. Lee H, Che W, Chatha K (2012) Dynamic scheduling of stream programs on embedded multi-core processors. In: Proc. Eighth IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis, pp 93–102. doi:10.1145/2380445.2380465

  17. Bonfietti A, Benini L, Lombardi M, Milano M (2010) An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms. In: Proc. Conference on Design, Automation and Test in Europe, pp 897–902. doi:10.1109/DATE.2010.5456924

  18. Wang Y, Liu H, Qin ZW et al (2011) Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip. ACM Trans Des Autom Electron Syst 16(2). doi:10.1145/1929943.1929946 (article no. 14)

  19. Zhang DS, Guo DK, Chen FY et al (2012) TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks. ACM Trans Archit Code Optim 8(4). doi:10.1145/2086696.2086726 (article no. 47)

  20. Liu C, Li J, Rubio J et al (2012) Power-efficient time-sensitive mapping in heterogeneous systems. In: Proc. 21st International Conference on Parallel architectures and compilation techniques, pp 23–32. doi:10.1145/2370816.2370822

  21. Boyd-Wickizer S, Chen HB, Chen R et al (2008) Corey: an operating system for Many Cores. In: Proc. 2008 USENIX Symposium on Operating Systems Design and Implementation, pp 43–57

  22. Peter S, Schüpbach A, Barham P et al (2010) Design principles for end-to-end multicore schedulers. In: Proc. Workshop on Hot Topics in Parallelism. http://www.barrelfish.org/barrelfish_hotpar10.pdf

  23. Bjerregaard T, Mahadevan S (2006) A survey of research and practices of Network-on-chip. ACM Comput Surv 38(1). doi:10.1145/1132952.1132953 (article no. 1)

  24. Wu J (2002) A deterministic fault-tolerant and deadlock-free routing protocol in 2-D meshes based on odd-even turn model. In: Proc. 16th International Conference on Supercomputing, pp 67–76. doi:10.1145/514191.514204

  25. Taktak S, Desbarbieux J, Encrenaz E (2008) A tool for automatic detection of deadlock in wormhole networks on chip. ACM Trans Des Autom Electron Syst 13(1):1–22. doi:10.1145/1297666.1297672

    Article  Google Scholar 

  26. Liu AH, Dick RP (2006) Automatic run-time extraction of communication graphs from multithreaded applications. In: Proc. fourth IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, pp 46–51. doi:10.1145/1176254.1176268

  27. Wind River Simics. http://www.windriver.com/products/simics/

  28. Hu W (2011) Scratchpad memory based power efficient optimization for MPSoC. In; Proc. 2011 International Conference on Electronics, Communications and Control, pp 455–458. doi:10.1109/ICECC.2011.6067865

  29. Cho D, Issenin I, Dutt N et al (2007) Software controlled memory layout reorganization for irregular array access patterns. In: Proc. 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp 179–188. doi:10.1145/1289881.1289915

  30. Noxim: Network-on-Chip simulator. https://github.com/davidepatti/noxim

  31. MINIX 3, A New Open-source microkernel OS. http://www.minix3.org

  32. Carvalho E, Calazans N, Moraes F (2007) Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs. In: Proc. 18th IEEE/IFIP International Workshop on Rapid System Prototyping, pp 34–40. doi:10.1109/RSP.2007.26

  33. Carvalho E, Moraes F (2008) Congestion-aware task mapping in heterogeneous MPSoCs. In: Proc. 2008 International Symposium on System-on-Chip, pp 1–4. doi:10.1109/ISSOC.2008.4694878

  34. Hu W, Tang XS, Xie B et al (2010) An efficient power-aware optimization for task scheduling on NoC-based many-core system. In: Proc. 10th IEEE International Conference on Computer and Information Technology, pp 171–178. doi:10.1109/CIT.2010.67

Download references

Acknowledgments

This work was supported by National Natural Science Foundation of China (Granted No. 61100055 and 61403287).

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Wei Hu.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Hu, W., Guo, H., Zhang, K. et al. An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system. J Supercomput 73, 3344–3365 (2017). https://doi.org/10.1007/s11227-016-1700-4

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-016-1700-4

Keywords

Navigation