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Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip

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Abstract

Mapping intellectual properties (IPs) on network-on-chip (NoC) has a notable impact on the timing, performance, and energy consumption of NoC. In this paper, we present a novel performance and power-aware task mapping technique based on mesh NoC that combines the latency constraint and branch and bound concepts. Our proposal for the definition of latency constraint helps intensify the bounds for pattern searching. With appropriate latency constraints, the best mapping solution can be achieved with less CPU time. This algorithm can be used with any NoC mesh shape. The mapping solutions are emulated on the FPGA-based NoC emulation platform. The experimental results demonstrate that the latency-constraint branch and bound technique can achieve better timing and lower energy consumption in nearly half the CPU time of the traditional branch and bound mapping algorithm.

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Acknowledgments

The research reported in this paper was supported by National High-tech Research and Development Projects (863) under Grant 2012AA012705, International Cooperation in Science and Technology Special Project of Ministry of Science and Technology of China under Grant 2012DFB10170, and China Scholarship Council under Grant 201306250116. And funding for this project was partly provided by a grant from la Région Rhône-Alpes as well as by the CNPq (process 245340/2012-2).

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Authors and Affiliations

  1. School of Computer Science and Technology, Tianjin University, 92 Weijin Road, Tianjin, 300072, China

    Ke Pang

  2. Laboratoire Hubert Curien, UMR CNRS 5516, Jean Monnet University, University de Lyon, 18 rue Benoit Lauras, 42000, Saint Etienne, France

    Virginie Fresse

  3. School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Tianjin, 300072, China

    Suying Yao

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  1. Ke Pang
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  2. Virginie Fresse
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  3. Suying Yao
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Correspondence to Ke Pang.

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Pang, K., Fresse, V. & Yao, S. Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip. J Supercomput 72, 2283–2309 (2016). https://doi.org/10.1007/s11227-016-1732-9

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  • DOI: https://doi.org/10.1007/s11227-016-1732-9

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