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Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems

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Abstract

Photonic networks-on-chip (PNoCs) have emerged as a promising alternative to the conventional metal-based networks-on-chip due to their advantages in bandwidth density, power efficiency and propagation speed. Existing works on PNoCs concentrate on architectures of photonic networks with the assumption that the underlying photonic infrastructure operates correctly and reliably. However, the key optical device in PNoC systems, microring resonators (MRs), is very sensitive to temperature fluctuation and manufacturing errors. A single MR failure can cause messages to be misdelivered or lost, which results in bandwidth loss or even complete failure of the whole system. In this paper, we present a fault-tolerant Photonic Network-on-Chip architecture, named FT-PHENIC, which uses minimal redundancy to ensure accuracy of packet transmission even after faulty microring resonators (MRs) are detected. FT-PHENIC is based on a microring fault-resilient photonic router (FTTDOR) and an adaptive path-configuration and routing algorithm. Simulation results show that FT-PHENIC tolerates MR faults quite well up until around when 20 % of the MRs have failed, and has minimal bandwidth degradation and power drawbacks.

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Acknowledgments

The authors are grateful to the reviewers who offer us helpful suggestions to improve this paper. This work is partially supported by the University of Aizu Competitive Research funding (CRF), Ref. P-11-2016.

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  1. Office: RQ 202-A, Adaptive Systems Laboratory, Graduate School of Computer Science and Engineering, The University of Aizu, Aizu-Wakamatsu, Fukushima, 965-8580, Japan

    Michael Meyer, Yuichi Okuyama & Abderazek Ben Abdallah

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  1. Michael Meyer
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  3. Abderazek Ben Abdallah
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Correspondence to Michael Meyer.

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This Project is supported by University of Aizu Competitive Research Fund, Ref. P-11-2016.

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Meyer, M., Okuyama, Y. & Abdallah, A.B. Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems. J Supercomput 73, 1567–1599 (2017). https://doi.org/10.1007/s11227-016-1846-0

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