Abstract
In the current paper, we propose a new online search, fault detection, and fault location approach for short faults in network on chip communication channels. The approach proposed consists of a built-in self-test as well as a packet/flit comparings module embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, firstly, the diagnosis and location processes are simultaneously carried out after which the test time is minimized. Secondly, the approach updates the NoC routing tables far less costly in a parallel fashion. Thirdly, insignificant hardware is added to the system. The high scalability in the approach, in addition, leads to 100% test coverage, 71.4% capability of detecting faulty channels, and 100% detected faults location in one round (two phases). The simulation results show that the approach hardware is optimized compared with the previous methodologies.










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References
Agarwal A, Iskander C, Shankar R (2009) Survey of network on chip (NoC) architectures & contributions. J Eng Comput Archit 3(1):21–27
De Micheli G, Benini L (2002) Networks on chip: a new paradigm for systems on chip design. In: Proceedings of IEEE Europe Conference & Exhibition in Design, Automation & Test, pp 0418
Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Elsevier, San Diego
Henkel J, Wolf W, Chakradhar S (2004) On-chip networks: a scalable, communication-centric embedded system design paradigm. In: Proceeding of IEEE 17th International Conference on VLSI Design, pp 845–851
Cota É, de Morais Amory A, Lubaszewski MS (2011) Reliability, availability and serviceability of networks-on-chip. Springer, New York
Behrouz RJ, Modarressi M, Sarbazi-Azad H (2014) Fault-tolerant routing algorithms in networks on-chip. In: Routing Algorithms in Networks-on-Chip. Springer, New York, pp 193–210
Ghofrani A, Parikh R, Shamshiri S, DeOrio A, Cheng K-T, Bertacco V (2012) Comprehensive online defect diagnosis in on-chip networks. In: VTS, pp 44–49
Cheng AC (2002) Comprehensive study on designing memory BIST: algorithms, implementations and trade-offs. Ann Arbor 1001:48109–52122
Grecu C, Pande P, Ivanov A, Saleh R (2006) BIST for network-on-chip interconnect infrastructures. In: Proceedings of 24th IEEE VLSI Test Symposium, pp 6–35
Cota EF, Kastensmidt FGdL, Santos MCd, Hervé MB, Almeida PRVd, Meirelles PRM, Amory AdM, Lubaszewski MS (2008) A high-fault-coverage approach for the test of data, control, and handshake interconnects in mesh networks-on-chip. IEEE Trans Comput N Y 57(9):1202–1215
Vermeulen B, Dielissen J, Goossens K, Ciordas C (2003) Bringing communication networks on a chip: test and verification implications. IEEE Commun Mag 41(9):74–81
Cota É, Carro L, Lubaszewski M (2004) Reusing an on-chip network for the test of core-based systems. ACM Trans Des Autom Electron Syst (TODAES) 9(4):471–499
Kim J-S, Hwang M-S, Roh S, Lee J-Y, Lee K, Lee S-J, Yoo H-J (2004) On-chip network based embedded core testing. In: Proceedings of IEEE International SOC Conference, pp 223–226
Aghaei B, Babaei S (2009) The new test wrapper design for core testing in packet-switched micro-network on chip. In: Proceedings 2nd International Conference on Power Electronics and Intelligent Transportation System (PEITS), pp 19–20
Ying Z, Ning W, Fen G, Xin C, Lei Z (2013) Novel core test wrapper design supporting multi-mode testing of NoC-based SoC. Int J Control Autom 6(5):247–262
Han T, Choi I, Oh H, Kang S (2014) A scalable and parallel test access strategy for NoC-based multicore system. In: Proceedings of IEEE 23rd Asian Test Symposium (ATS), pp 81–86
Amory AM, Goossens K, Marinissen EJ, Lubaszewski M, Moraes F (2007) Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput Digit Tech 1(3):197–206
Nazarian G (2008) On-line testing of routers in networks-on-chip. TU Delft, Delft University of Technology
Babaei S, Mansouri M, Aghaei B, Khadem-Zadeh A (2011) Online-structural testing of routers in network on chip. World Appl Sci J 14(9):1374–1383
Cota É, de Morais Amory A, Lubaszewski MS (2012) Test and diagnosis of routers. In: Reliability, Availability and Serviceability of Networks-on-Chip. Springer, pp 115–132
Nazari M, Zolfy Lighvan M, Daie Koozekonani Z, Sadeghi A (2016) A novel HW/SW based NoC router self-testing methodology. arXiv preprint arXiv:1609.04569
Alamian SS, Fallahzadeh R, Hessabi S, Alirezaie J (2013) A novel test strategy and fault-tolerant routing algorithm for NoC routers. In: Proceedings of IEEE 17th CSI International Symposium on Computer Architecture & Digital Systems, pp 133–136
Hosseinabady M, Dalirsani A, Navabi Z (2007) Using the inter-and intra-switch regularity in NoC switch testing. In: Proceedings European Conference on Design, Automation and Test in, pp 361–366
Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online NoC switch fault detection and diagnosis using a high level fault model. In: Proceedings of 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp 21–29
Kautz WH (1974) Testing for faults in wiring networks. IEEE Trans Comput 100(4):358–363
Hassan A, Rajski J, Agarwal VK (1988) Testing and diagnosis of interconnects using boundary scan architecture. In: Proceedings of IEEE International Test Conference New Frontiers in Testing, pp 126–137
Lien J-C, Breuer MA (1991) Maximal diagnosis for wiring networks. In: ITC, pp 96–105
Krstic A, Cheng K-T (1998) Delay fault testing for VLSI circuits, vol 14. Springer, New York
Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault modeling and simulation for crosstalk in system-on-chip interconnects. In: Proceedings IEEE/ACM International Conference on Computer-Aided Design, pp 297–303
Ubar R, Raik J (2003) Testing strategies for networks on chip. In: Networks on chip. Springer, pp 131–152
Petersén K, Öberg J Toward (2007) A scalable test methodology for 2D-mesh network-on-chips. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp 367–372
Herve M, Cota E, Kastensmidt FL, Lubaszewski M (2009) Diagnosis of interconnect shorts in mesh NoCs. In: Proceedings 3rd ACM/IEEE International Symposium on Networks-on-Chip, pp 256–265
Concatto C, Almeida P, Kastensmidt F, Cota E, Lubaszewski M, Herve M (2009) Improving yield of torus NoCs through fault-diagnosis-and-repair of interconnect faults. In: Proceedings of 15th IEEE International On-Line Testing Symposium, pp 61–66
Hervé M, Almeida P, Kastensmidt FL, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proceedings of 11th Latin American Test Workshop
Strano A, Gómez C, Ludovici D, Favalli M, Gómez ME, Bertozzi D (2011) Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In: Proceedings of IEEE European Design, Automation & Test, pp 1–6
Kakoee MR, Bertacco V, Benini L (2011) A distributed and topology-agnostic approach for on-line NoC testing. In: Proceedings Fifth ACM/IEEE International Symposium on Networks-on-Chip, pp 113–120
Kakoee MR, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in NoCs. IEEE Trans Comput 63(3):703–717
Bhowmik B, Deka JK, Biswas S (2015) An odd-even model for diagnosis of shorts on NoC interconnects. In: Proceedings of 2015 Annual IEEE India Conference (INDICON), pp 1–6
Bhowmik B, Biswas S, Deka JK (2016) Impact of NoC interconnect shorts on performance metrics. In: Proceedings of IEEE Twenty Second National Conference on Communication (NCC), pp 1–6
Bhowmik B, Deka JK, Biswas S (2016) An on-line test solution for addressing interconnect shorts in on-chip networks. In: Proceedings of IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp 9–12
Stroud CE (2002) A designer’s guide to built-in self-test, vol 19. Springer, New York
Xilinx I (2014) Design suite 14.4: release notes. Installation, and licensing
Spartan XD (2013) 3E FPGA family data sheet. DS312 July 19
Fick D, DeOrio A, Hu J, Bertacco V, Blaauw D, Sylvester D (2009) Vicis: a reliable network for unreliable silicon. In: Proceedings of 46th ACM Annual Design Automation Conference, pp 812–817
Goossens K, Dielissen J, Radulescu A (2005) Æthereal network on chip: concepts, architectures, and implementations. IEEE Des Test Comput 22(5):414–421
Moraes F, Calazans N, Mello A, Möller L, Ost L (2004) HERMES: an infrastructure for low area overhead packet-switching networks on chip. VLSI J Integr 38(1):69–93
Zeferino CA, Kreutz ME, Susin AA (2004) RASoC: A router soft-core for networks-on-chip. In: Proceedings of IEEE Design, Automation and Test in Europe Conference and Exhibition, pp 198–203
Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2015) Noxim: an open, extensible and cycle-accurate network on chip simulator. In: Proceedings of IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp 162–163
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Aghaei, B., Badie, K., Khademzadeh, A. et al. The cost-effective fault detection and fault location approach for communication channels in NoC. J Supercomput 73, 5034–5052 (2017). https://doi.org/10.1007/s11227-017-2070-2
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DOI: https://doi.org/10.1007/s11227-017-2070-2