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An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads

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Abstract

This paper focuses on energy consumption which is a major problem in the dark silicon era. As energy consumption becomes a key issue for operation and maintenance of cloud data centers, cloud computing providers are becoming significantly concerned. Here, we show how spin-transfer torque random access memory (STT-RAM) can be used as an on-chip L2 cache to obtain lower energy compared to conventional L2 caches, like SRAM. High density, fast read access and non-volatility make STT-RAM a significant technology for on-chip memories. Previous studies have mainly studied specific schemes based on common applications and do not provide a thorough analysis of emerging scale-out applications with multiple design options. Here, we discuss different outlooks consisting of performance and energy efficiency in cloud processors by running emerging scale-out workloads. Experiment results on the CloudSuite benchmarks show that the proposed method reduces energy by 51% (on average) and improves energy delay product by 37% (on average) where instruction per cycle degradation is only 22% (on average) compared to the SRAM method.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Adnan Nasri

  2. Department of Computer Engineering, Iran University of Science and Technology, Tehran, Iran

    Mahmood Fathy

  3. Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran

    Ali Broumandnia

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  1. Adnan Nasri
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  2. Mahmood Fathy
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  3. Ali Broumandnia
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Correspondence to Mahmood Fathy.

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Nasri, A., Fathy, M. & Broumandnia, A. An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads. J Supercomput 74, 1547–1561 (2018). https://doi.org/10.1007/s11227-017-2180-x

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