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Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip

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Abstract

Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips are stacked side-by-side on a silicon interposer layer in the 2.5D stacking technology. 2.5D stacking can solve many of the 3D stacking difficulties such as thermal problem. The cores in the processing element (PE) layer must have the ability to connect together. Moreover, the connection between the processing cores and the other chips is a critical issue that should be concerned. The memory chip is one of the most important chips, integrated with the many-core chip. The network-on-chip can be extended to the interposer layer to increase the usability of the interposer layer. It is essential to have an efficient topology and deadlock-free routing algorithm to handle operations effectively and decrease delay and power consumption. In this paper, a new topology called “Balanced Mesh” and a deadlock-free routing algorithm is recommended that balances fairly the connection between different Mesh-based segments of a network. Many of interposer network topologies such as ButterDonut increase the degree of intermediate routers in the interposer layer or nodes related to other chips. Many of them cannot be easily used in the PE layer to have a uniform system. The proposed topology can be simply applied to both of many-core layer and the interposer layer to decrease delay and power consumption without any change in the degree of nodes and has lesser number of links. Our proposed topology is compared with some other topologies such as concentrated Mesh(CMesh) and ButterDount. Simulation results show that our proposed topology can improve the system efficiency with lesser number of links. Using our proposed topology in both layers achieves 13% improvement in network latency compared with using Mesh in the PE layer and ButterDonut in the interposer layer. Also, it achieves 12% improvement in power consumption.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Sajed Dadashi & Midia Reshadi

  2. Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

    Akram Reza

  3. Iran Telecommunication Research Center, Tehran, Iran

    Ahmad Khademzadeh

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  1. Sajed Dadashi
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  2. Akram Reza
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  3. Midia Reshadi
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  4. Ahmad Khademzadeh
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Correspondence to Akram Reza.

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Dadashi, S., Reza, A., Reshadi, M. et al. Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip. J Supercomput 75, 7646–7664 (2019). https://doi.org/10.1007/s11227-019-02964-w

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