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Efficient binary to quaternary and vice versa converters: embedding in quaternary arithmetic circuits

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Abstract

Reversible logic is a nowadays promising choice for circuit design technologies since it is having diversified applications in the fields of digital signal processing, cryptography, quantum computing, and low power CMOS design. Since every two qubits in the binary logic are equivalent to one qudit in the quaternary logic, the optimum designed primary binary building blocks such as adders and subtractors easily can be used in quaternary logic design. In this paper, we first proposed a novel quaternary to a binary decoder and also binary to quaternary encoder circuits. Secondly, we have used these converters to the synthesis of the quaternary quantum reversible full adder, half subtractor, and full subtractor circuits. The proposed converter circuits have promised accomplishment compared to the existing designs; these circuits are built on the elementary quantum gates, which are realizable using the liquid ion trap in the quantum technology. The designed strategy (using the converters to realize computational circuits) is easily applicable in the large-scale quaternary quantum circuit designs.

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References

  1. Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 5(3):183–191

    Article  MathSciNet  Google Scholar 

  2. Maslov D (2003) Reversible logic synthesis. Ph.D. thesis, The Faculty of Computer Science, The University of New Brunswick, Canada

  3. Dueck GW, Maslov D (2003) Reversible function synthesis with minimum garbage outputs. In: Proceedings of the 6th international symposium on representations and methodology of future computing technologies (RM 2003), Trier, Germany, pp 154–161

  4. Maslov D, Dueck GW (2003) Garbage in reversible designs of multiple output functions. In: Proceedings of the 6th international symposium on representations and methodology of future computing technologies (RM 2003), Trier, Germany, pp 162–170

  5. Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17:525–532

    Article  MathSciNet  Google Scholar 

  6. Thapliyal H, Kotiyal S, Srinivas MB (2006) Novel BCD adders and their reversible logic implementation for IEEE 754r format. In: Proceedings of the IEEE 19th International Conference on VLSI Design (VLSID’06), Hyderabad, India, pp 387–392

  7. Lukac M, Pivtoraiko M, Mishchenko A, Perkowski M (2002) Automated synthesis of generalized reversible cascades using genetic algorithms. In: 5th international workshop on boolean problems, Freiburg, Germany, pp 33–45

  8. Perkowski M, Jozwiak L, Kerntopf P, Mishchenko A, Al-Rabadi A, Coppola A et al. (2001) A general decomposition for reversible logic. Proc. RM’2OO1 Starkville, pp. 119–138

  9. Perkowski M, Kerntopf P (2001) Reversible logic. Invited tutorial. Proc. EURO-MICRO

  10. Babu HMH, Chowdhury AR (2005) Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In: 18th International Conference on VLSI Design Held Jointly with 4th International Conference on Embedded Systems Design. IEEE, pp 255–260‏

  11. Curtis E, Perkowski M (2004) A transformation based algorithm for ternary reversible logic synthesis using universally controlled ternary gates. Proc IWLS 2004:345–352

    Google Scholar 

  12. Doshanlou AN, Haghparast M, Hosseinzadeh M, Reshadi M (2019) Efficient design of quaternary quantum comparator with only a single ancillary input. IET Circuits Devices Syst 14(1):80–87

    Article  Google Scholar 

  13. Khan MH, Perkowski MA, Khan MR, Kerntopf P (2005) Ternary GFSOP minimization using kronecker decision diagrams and their synthesis with quantum cascades. J Multiple-Valued Logic Soft Comput 11(5/6):567

    MATH  Google Scholar 

  14. Khan MH, Perkowski MA, Khan MR (2004) Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]. In: 34th International Symposium on Multiple-valued Logic, 2004. Proceedings. IEEE, pp 58–67.‏

  15. Khan MH, Perkowski M (2005) Quantum realization of ternary encoder and decoder. In: Proceedings of 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM2005), Tokyo, Japan

  16. Khan MH (2006) Design of reversible/quantum ternary multiplexer and demultiplexer. Eng Lett 13(2):65–69

    Google Scholar 

  17. Kalantari Z, Eshghi M, Mohammadi M et al (2019) Low-cost and compact design method for reversible sequential circuits. J Supercomput 75:7497–7519

    Article  Google Scholar 

  18. Arabzadeh M, Saeedi M (2018) RCViewer+: a viewer/analyzer for reversible and quantum circuits

  19. Doshanlou AN, Haghparast M, Hosseinzadeh M, Reshadi M (2019) Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor. Int J Quantum Inf 17(05):1950048

    Article  MathSciNet  Google Scholar 

  20. Saeedi M, Markov IL (2013) Synthesis and optimization of reversible circuits–a survey. ACM CSUR 45(2):21

    MATH  Google Scholar 

  21. Norouzi Doshanlou A, Haghparast M, Hosseinzadeh M (2019) Novel quaternary quantum reversible half adder and full adder circuits. IETE J Res. https://doi.org/10.1080/03772063.2019.1656554

    Article  MATH  Google Scholar 

  22. Khan MH, Perkowski MA (2007) GF (4) based synthesis of quaternary reversible/quantum logic circuits. In: 37th IEEE international symposium on multiple-valued logic (ISMVL'07), pp 11–11‏

  23. Khan MH (2008) A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry. J Syst Architect 54(12):1113–1121

    Article  Google Scholar 

  24. Mandal SB, Chakrabarti A, Sur-Kolay S (2012) A synthesis method for quaternary quantum logic circuits. In: Progress in VLSI design and test. Springer, Berlin, pp 270–280‏

  25. Khoshkhahesh A, Ebrahimi S, Sabbaghi-Nadooshan R (2018) Designing and optimizing DNA reversible adders and adder/subtractors. BioNanoScience 8(1):118–130

    Article  Google Scholar 

  26. Haghparast M, Navi K (2008) A Novel reversible BCD adder for nanotechnology-based systems. Am J Applied Sci 5(3):282–288

    Article  Google Scholar 

  27. Orts F, Ortega G, Garzón EM (2019) A faster half subtractor circuit using reversible quantum gates. Baltic J Modern Comput 7(1):99–111

    Article  Google Scholar 

  28. Monfared AT, Haghparast M, Datta K (2019) Quaternary quantum/reversible half-adder, full-adder, parallel adder and parallel adder/subtractor circuits. Int J Theor Phys 58:2184–2199. https://doi.org/10.1007/s10773-019-04108-5

    Article  MathSciNet  Google Scholar 

  29. Haghparast M, Monfared AT (2018) Designing novel quaternary quantum reversible subtractor circuits. Int J Theor Phys 57(1):226–237

    Article  MathSciNet  Google Scholar 

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Abdollah Norouzi Doshanlou & Midia Reshadi

  2. Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

  3. Institute of Research and Development, Duy Tan University, Da Nang, 550000, Vietnam

    Mehdi Hosseinzadeh

  4. Computer Science, University of Human Development, Sulaymaniyah, Iraq

    Mehdi Hosseinzadeh

Authors
  1. Abdollah Norouzi Doshanlou
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  2. Majid Haghparast
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  3. Mehdi Hosseinzadeh
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  4. Midia Reshadi
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Correspondence to Majid Haghparast.

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Norouzi Doshanlou, A., Haghparast, M., Hosseinzadeh, M. et al. Efficient binary to quaternary and vice versa converters: embedding in quaternary arithmetic circuits. J Supercomput 77, 14600–14616 (2021). https://doi.org/10.1007/s11227-021-03696-6

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  • DOI: https://doi.org/10.1007/s11227-021-03696-6

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