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Analysing software prefetching opportunities in hardware transactional memory

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Abstract

Hardware transactional memory emerged to make parallel programming more accessible. However, the performance pitfall of this technique is squashing speculatively executed instructions and re-executing them in case of aborts, ultimately resorting to serialization in case of repeated conflicts. A significant fraction of aborts occurs due to conflicts (concurrent reads and writes to the same memory location performed by different threads). Our proposal aims to reduce conflict aborts by reducing the window of time during which transactional regions can suffer conflicts. We achieve this by using software prefetching instructions inserted automatically at compile-time. Through these prefetch instructions, we intend to bring the necessary data for each transaction from the main memory to the cache before the transaction itself starts to execute, thus converting the otherwise long latency cache misses into hits during the execution of the transaction. The obtained results show that our approach decreases the number of aborts by 30% on average and improves performance by up to 19% and 10% for two out of the eight evaluated benchmarks. We provide insights into when our technique is beneficial given certain characteristics of the transactional regions, the advantages and disadvantages of our approach, and finally, discuss potential solutions to overcome some of its limitations.

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Notes

  1. If a function is called in two different transactions, we create one AP version for each call context. AP versions are transaction specific because the selection of the instructions for each AP depends on how the memory updates performed within the function affect its callers.

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Funding

This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No 819134), the Spanish MCIU and AEI, as well as the European Commission FEDER funds, under grant RTI2018-098156-B-C53, and the Swedish VR grant number 2016-05086.

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Authors and Affiliations

  1. Department of Computing Systems, Uppsala University, Uppsala, Sweden

    Marina Shimchenko, Stefanos Kaxiras & Alexandra Jimborean

  2. Computer Engeneering Department, University of Murcia, Murcia, Spain

    Rubén Titos-Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros & Alexandra Jimborean

Authors
  1. Marina Shimchenko
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  2. Rubén Titos-Gil
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  3. Ricardo Fernández-Pascual
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  4. Manuel E. Acacio
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  5. Stefanos Kaxiras
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  6. Alberto Ros
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  7. Alexandra Jimborean
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Corresponding author

Correspondence to Alberto Ros.

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Shimchenko, M., Titos-Gil, R., Fernández-Pascual, R. et al. Analysing software prefetching opportunities in hardware transactional memory. J Supercomput 78, 919–944 (2022). https://doi.org/10.1007/s11227-021-03897-z

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