Skip to main content
SpringerLink
Log in

NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

Regarding the increase in the number of cores in the electronic network-on-chip, they may not be an ideal choice in the response of needing latency, power, and reliability. However, this problem has been effectively solved by proposing photonic network-on-chips (PNoCs). The optical routers play an indispensable role in the PNoCs. So far, multiple routers for different architectures of PNoC have been proposed. The most of optical routers are based on micro-ring resonators (MRRs), while Mach–Zehnder interferometers (MZIs) are preferable for optical router design due to their high thermal tolerance and potential for large capacity. In this research, a 4 × 4 non-blocking optical router based on Mach–Zehnder interferometer is proposed. The router is designed for a deadlock-free North-Last turning model, called NLR-OP. The NLR-OP non-blocking optical router is extended to improve network performance and physical layer parameters for a wide range of silicon nano-photonic multicore interconnection topologies. Moreover, assigning 30 dB to the optical power budget for interconnection using the NLR-OP router allows the Non-blocking Torus to expand to 196 nodes. Compared to previously reported router designs, this router design allows quantifying the improvement in system performance parameters in terms of insertion loss for well-known photonic interconnection topologies. For instance, applying the NLR-OP optical router in the Non-blocking Torus topology leads to a 38% reduction insertion loss in comparison with the previously highest performing optical router design. The routing performance of this router is simulated by the successful transmission of a 20-Gbps optical signal at the wavelength range of 1548 nm to 1557 nm for each qualified port from a choice of 10 possible physical links.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26

Similar content being viewed by others

References

  1. Kulkarni A, Page A, Attaran N et al (2017) An energy-efficient programmable manycore accelerator for personalized biomedical applications. IEEE Trans Very Large Scale Integration (VLSI) Syst 26:96–109

  2. Pullini A, Conti F, Rossi D et al (2017) A heterogeneous multicore system on chip for energy efficient brain inspired computing. IEEE Trans Circuits Syst II Express Briefs 65:1094–1098

    Article  Google Scholar 

  3. Lerner S, Yilmaz I, Taskin B (2018) Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. IEEE Trans Very Large Scale Integration (VLSI) Syst 27:700–710

  4. Urbina M, Acosta T, Lázaro J et al (2019) Smart Sensor: SoC architecture for the Industrial Internet of Things. IEEE Internet Things J 6:6567–6577

    Article  Google Scholar 

  5. Pullini A, Rossi D, Loi I et al (2019) Mr. wolf: an energy-precision scalable parallel ultra low power soc for iot edge processing. IEEE J Solid-State Circuits 54:1970–1981

    Article  Google Scholar 

  6. Taheri E, Kim RG, Nikdast M (2021) AdEle: an adaptive congestion-and-energy-aware elevator selection for partially connected 3D NoCs. arXiv preprint arXiv:210208323

  7. Boroumand B, Yaghoubi E, Barekatain B (2020) An enhanced cost-aware mapping algorithm based on improved shuffled frog leaping in network on chips. J Supercomput, 1–25

  8. Khoroush S, Reshadi M, Khademzadeh A (2018) Application mapping in hybrid photonic networks-on-chip for reducing insertion loss. J Supercomput 74:4647–4671

    Article  Google Scholar 

  9. Liang L, Zhang K, Zheng CT et al (2017) N×N reconfigurable nonblocking polymer/silica hybrid planar optical switch matrix based on total-internal-reflection effect. IEEE Photonics J 9:1–11

    Google Scholar 

  10. Vahidifar S, Reshadi M (2017) Loss-aware routing algorithm for photonic networks on chip. J Supercomput 73:5496–5514

    Article  Google Scholar 

  11. Ben AA, Ben AA (2015) Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems. J Supercomput 71:4446–4475

    Article  Google Scholar 

  12. Reza A, Sarbazi-Azad H, Khademzadeh A et al (2014) A loss aware scalable topology for photonic on chip interconnection networks. J Supercomput 68:106–135

    Article  Google Scholar 

  13. Sunny F, Mirza A, Thakkar I et al (2020) LORAX: Loss-aware approximations for energy-efficient silicon photonic networks-on-chip. In: Proceedings of the 2020 on Great Lakes Symposium on VLSI, pp 235–240

  14. Bagheri Renani N, Yaghoubi E (2018) A review of optical routers in photonic networks-on-chip: a literature survey. J Adv Comput Eng Technol 4:143–154

    Google Scholar 

  15. Hesham S, Rettkowski J, Goehringer D, Abd El Ghany MA (2016) Survey on real-time networks-on-chip. IEEE Trans Parallel Distrib Syst 28:1500–1517

    Article  Google Scholar 

  16. Shacham A, Bergman K, Carloni LP (2008) Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans Comput 57:1246–1260

    Article  MathSciNet  Google Scholar 

  17. Lu L, Zhou L, Li Z et al (2015) Broadband 4×4 nonblocking Silicon electrooptic switches based on Mach-Zehnder interferometers. IEEE Photonics J 7:1–8

    Google Scholar 

  18. Guo Z, Lu L, Zhou L et al (2017) 16× 16 silicon optical switch based on dual-ring-assisted Mach-Zehnder interferometers. J Lightwave Technol 36:225–232

    Article  Google Scholar 

  19. Dupuis N, Lee BG, Rylyakov AV et al (2015) Design and fabrication of low-insertion-loss and low-crosstalk broadband $2\times 2$ Mach-Zehnder silicon photonic switches. J Lightwave Technol 33:3597–3606

    Article  Google Scholar 

  20. Shabani H, Roohi A, Reza A et al (2015) Loss-aware switch design and non-blocking detection algorithm for intra-chip scale photonic interconnection networks. IEEE Trans Comput 65:1789–1801

    Article  MathSciNet  Google Scholar 

  21. Chan J, Biberman A, Lee BG, Bergman K (2008) Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications. In: LEOS 2008–21st Annual Meeting of the IEEE Lasers and Electro-Optics Society. IEEE, pp 300–301

  22. Yaghoubi E, Reshadi M, Hosseinzadeh M (2015) Mach–Zehnder-based optical router design for photonic networks on chip. Opt Eng 54:35102

    Article  Google Scholar 

  23. Shacham A, Lee BG, Biberman A, et al (2007) Photonic NoC for DMA communications in chip multiprocessors. In: 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007). IEEE, pp 29–38

  24. Bergman K, Carloni LP, Biberman A et al (2014) Photonic network-on-chip design. Springer, Heidelberg

    Book  Google Scholar 

  25. Yang Y, Chen K, Gu H et al (2018) TAONoC: A regular passive optical network-on-chip architecture based on comb switches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27:954–963

  26. Yang M, Green WMJ, Assefa S et al (2011) Non-blocking 4x4 electro-optic silicon switch for on-chip photonic networks. Opt Express 19:47–54

    Article  Google Scholar 

  27. Geng M, Tang Z, Chang K et al (2017) N-port strictly non-blocking optical router based on Mach-Zehnder optical switch for photonic networks-on-chip. Opt Commun 383:472–477

    Article  Google Scholar 

  28. Liu K, Wang L, Zhang C et al (2018) Compact InGaAsP/InP nonblocking 4×4 trench-coupler-based Mach-Zehnder photonic switch fabric. Appl Opt 57:3838–3846

    Article  Google Scholar 

  29. Ye T, Ding J, Lee TT, Maier G (2020) AWG-based nnonblocking Shuffle-exchange networks. IEEE/ACM Trans Netw 28:2699–2712

    Article  Google Scholar 

  30. Fadhel M, Huang L, Gu H (2020) RRW: a reliable ring waveguide-based optical router for photonic network-on-chip. In: International Symposium on Parallel Architectures, Algorithms and Programming, pp 429–438

  31. Yahya MR, Wu N, Zhou F et al (2020) SMOR: design of an optimized 5×5 nonblocking optical router for photonic NoCs constructed via silicon microring optical switch. Opt Eng 59:46104

    Article  Google Scholar 

  32. Lin J, Pengfei C, Rui S, Haoyue W (2020) MSONoC: a non-blocking optical interconnection network for inter cluster communication. High Technol Lett, 262–269

  33. Asadinia S, Mehrabi M, Yaghoubi E (2020) Surix: Non-blocking and low insertion loss micro-ring resonator-based optical router for photonic network on chip. J Supercomput, pp 1–23

  34. Bahadori M, Rumley S, Polster R, Bergman K (2016) Loss and crosstalk of scalable MZI-based switch topologies in silicon photonic platform. In: 2016 IEEE Photonics Conference (IPC). IEEE, pp 615–616

  35. Wang H, Petracca M, Biberman A et al (2008) Nanophotonic optical interconnection network architecture for on-chip and off-chip communications. In: Optical Fiber Communication Conference. Optical Society of America, p JThA92

  36. Chan J, Hendry G, Biberman A, Bergman K (2010) Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis. J Lightwave Technol 28:1305–1315

    Article  Google Scholar 

  37. Beneš VE (1962) Algebraic and topological properties of connecting networks. Bell Syst Tech J 41:1249–1274

    Article  MathSciNet  Google Scholar 

  38. Wu Y, Lu C, Chen Y (2016) A survey of routing algorithm for mesh Network-on-Chip. Front Comp Sci 10:591–601

    Article  Google Scholar 

  39. Asadi B, Reshadi M, Khademzadeh A (2017) A routing algorithm for reducing optical loss in photonic Networks-on-Chip. Photon Netw Commun 34:52–62

    Article  Google Scholar 

  40. Chan JW (2012) Architectural exploration and design methodologies of photonic interconnection networks. Columbia University

  41. Lu L, Zhao S, Zhou L et al (2016) 16× 16 non-blocking silicon optical switch based on electro-optic Mach-Zehnder interferometers. Opt Express 24:9295–9307

    Article  Google Scholar 

  42. Zhao S, Lu L, Zhou L et al (2016) 16× 16 silicon Mach-Zehnder interferometer switch actuated with waveguide microheaters. Photonics Research 4:202–207

    Article  Google Scholar 

  43. Thakkar IG, Pasricha S (2018) LIBRA: Thermal and process variation aware reliability management in photonic networks-on-chip. IEEE Trans Multi-Scale Comput Syst 4:758–772

    Article  Google Scholar 

  44. Xia F, Sekaric L, Vlasov Y (2007) Ultracompact optical buffers on a silicon chip. Nat Photonics 1:65–71

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Negin Bagheri Renani & Elham Yaghoubi

  2. Big Data Research Centre, Najafabad Branch, Islamic Azad University, Najafabad, Iran

    Negin Bagheri Renani & Elham Yaghoubi

  3. Faculty of Technical and Engineering, Karoon Institute of Higher Education, Ahwaz, Iran

    Naser Sadehnezhad

  4. Department of Computer Engineering, Shabestar Branch, Islamic Azad University, Shabestar, Iran

    Tofigh Abbasi

Authors
  1. Negin Bagheri Renani
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Elham Yaghoubi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Naser Sadehnezhad
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Tofigh Abbasi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Elham Yaghoubi.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Renani, N.B., Yaghoubi, E., Sadehnezhad, N. et al. NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors. J Supercomput 78, 2442–2476 (2022). https://doi.org/10.1007/s11227-021-03920-3

Download citation

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-021-03920-3

Keywords

Search

Navigation