Abstract
The two-dimensional guided filter is a linear time-varying filter that can filter the noise and retain the detailed information of the image better. It is widely used in image denoising. However, in its application process, it is necessary to calculate the parameters required by filtering in real time according to the data. The operation process involves complex floating point multiplication and division operations, which leads to the high complexity of hardware implementation and excessive resource overhead. It is also difficult to improve the comprehensive speed of the system, which is not good for real-time signal processing. Aiming at the above problems, based on the theory of guided filtering and taking full advantage of the parallelism of FPGA, we proposed a two-dimensional guided filter hardware optimization system based on FPGA. In the system, first, the original image data are cached in real time to reduce the occupation of other hardware resources. Then, the complex mean and variance operations are split into simple sum operations, which reduces the computational complexity. Finally, the system is designed by using serial and parallel flow operation methods, which effectively improve the operation speed of the system. The results show that the operating frequency of the optimized hardware system is up to 146.953 MHz, which is 28.322 MHz higher than that of the original guided filtering algorithm.
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Tang, X., Liu, W., Ren, J. et al. An optimized hardware design of a two-dimensional guide filter and its application in image denoising. J Supercomput 78, 8445–8466 (2022). https://doi.org/10.1007/s11227-021-04044-4
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DOI: https://doi.org/10.1007/s11227-021-04044-4