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Power efficient network selector placement in control plane of multiple networks-on-chip

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Abstract

Multiple networks-on-chip is a popular on-chip interconnect. This parallel communication infrastructure uses more than one NoCs to facilitate customized traffic distribution. Parallel architectures improve performance, however, at the cost of huge power dissipation. We propose power efficient customized placement of network selector hardware unit in the control plane at router. A network selector hardware unit is essentially used to distribute traffic between NoCs. Conventionally, this unit is placed in the data plane at network interface. We place network selector at switch allocator and at the routing unit of the router. The placement at switch allocator is more efficient than placement at routing unit or network interface. It improves 21% static power, 29% dynamic power, and 33% critical path delay of the circuit over network interface placement.

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Notes

  1. Gem5 simulator is an integration of M5 and GEMS simulators [13, 14]. M5 supports CPU models, Instruction Set Architecture (ISAs), input/output devices, infrastructure, whereas GEMS supports interconnect models including cache coherence protocols.

  2. The physical capacitance can be minimized in a number of ways, including circuit style selection, transistor sizing, placement and routing, and architectural optimizations [46]. These being a part of the fabrication, hence beyond the scope of this paper.

  3. We synonymously use the term control plane or control path.

  4. 3 and 4-bits, for our proposed architecture.

  5. 128/256/512-bits (128-bits for our proposed architecture).

  6. Recent NoC architectures are using higher bandwidth networks (for example, a link width of 512 bits is required to sustain modern per-core bandwidth [49]) So the placement in data path significantly increases hardware overheads.

  7. Here, \(I_{NI}\) is the number of NI links, which are the inputs to the router, and \(I_{R}\) is the number of inputs from other routers.

  8. We place Net-Demux only for one NoC as another NoC already has separate traffic.

  9. FLow control unITs.

  10. Five flits for our NoC architecture.

  11. Where K and N are the number of input bits.

  12. Refer to Sect. 3.2.

  13. refer to Sect. 3.1.

  14. Switching activity has two components (1) a static component—the function of the logic’s topology, and (2) a dynamic component—the function of the timing behavior (glitching). We have not discussed the dynamic part in detail as it is out of the scope of the paper.

  15. Low Voltage Threshold [50].

  16. The actual area advantage would be more for SA over NI. We get these area results when we have skipped the virtual channels and virtual networks in the circuit.

  17. The crossbar of the router dominates the critical path of the router.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, National Institute of Technology, Raipur, India

    Sonal Yadav

  2. Department of Computer Science and Engineering, Indian Institute of Information Technology, Kota, India

    Sonal Yadav

  3. Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Kota, India

    Ritu Raj

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  1. Sonal Yadav
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Yadav, S., Raj, R. Power efficient network selector placement in control plane of multiple networks-on-chip. J Supercomput 78, 6664–6695 (2022). https://doi.org/10.1007/s11227-021-04098-4

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