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Design and implementation of efficient QCA full-adders using fault-tolerant majority gates

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Abstract

CMOS technology is facing physical limitations in scaling the manufacturing process. Therefore, to deepen the development of better designs in a smaller area, it is necessary to look for other alternatives. One of the most studied approaches is Quantum Cellular Automata (QCA). However, it has the disadvantage of its reliability during the manufacturing processes, with high error rates that are difficult to improve. To contribute to the design of more reliable operators based on this technology, new fault-tolerant full-adders are presented in this paper. The proposed solutions improve area up to 57.14%, total energy dissipation up to 36.27%, and average energy dissipation per cycle up to 36.22% compared to those previously proposed. This reduction in power consumption is especially important to make QCA more competitive as it has to operate in low-temperature environments.

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Notes

  1. To obtain the results, QCADesigner has been used. The QCADesigner-E (QD-E) is an extension of the QCADesigner. It calculates the estimation of the power dissipation of QCA circuits. It is integrated as an additional simulation module that is based on the Coherence Vector Simulation (CVSE) [9, 10]

  2. Note that, comparisons to CMOS technology are omitted as it is outside of this work’s scope and is already analyzed in the literature by other authors.

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Authors and Affiliations

  1. ARIES Research Center, Universidad Antonio de Nebrija, Madrid, 28049, Spain

    J. A. Bravo-Montes, A. Martín-Toledano, A. Sánchez-Macián, O. Ruano & F. Garcia-Herrero

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  1. J. A. Bravo-Montes
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Bravo-Montes, J.A., Martín-Toledano, A., Sánchez-Macián, A. et al. Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. J Supercomput 78, 8056–8080 (2022). https://doi.org/10.1007/s11227-021-04247-9

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