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Data block manipulation for error rate reduction in STT-MRAM based main memory

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Abstract

Downscaling of semiconductor technology has led DRAM-based main memories to lag behind emerging non-volatile memories, e.g., Spin-Transfer Torque Magnetic Random-Accesses Memory (STT-MRAM). Although using STT-MRAMs reduces the issues with technology scaling, the common read/write path and stochastic switching lead to write failure (WF) and read disturbance (RD), which degrades their reliability. In STT-MRAMs, 0 → 1 transitions are the predominant cause of WF, and RD is associated only with cells storing "1." This paper proposes a low-cost microarchitectural technique to mitigate WF and RD in STT-MRAMs. By eliminating 0 → 1 transitions in write operations via prewriting the blocks and using an effective encoding to reduce the number of "1"s in read operations, we improve the reliability. The simulation results show an increase in mean time to WF by 3230% and reduction in RD rate by 22%. Reliability is enhanced by imposing only 0.1%, 1.52%, and 1.19% area, power consumption, performance overheads, respectively.

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References

  1. Aboutalebi A, Ahn EC, Mao B, Wu S, Duan L (2018) Mitigating and tolerating read disturbance in STT-MRAM-based main memory via device and architecture innovations. IEEE Trans Comput-Aided Des Integr Circuits Syst 38(12):2229–2242. https://doi.org/10.1109/TCAD.2018.2878166

    Article  Google Scholar 

  2. Lee B, Ipek E, Mutlu O, Burger D (2009) Architecting phase change memory as a scalable dram alternative. ACM SIGARCH Comput Archit News 37(3):2–13. https://doi.org/10.1145/1555754.1555758

    Article  Google Scholar 

  3. Komalan M, Rock O. H, Hartmann M, Sakhare S, Tenllado C (2018) Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 103–108. Doi: https://doi.org/10.23919/DATE.2018.8341987

  4. Khajekarimi E, Jamshidi K, Vafaei A (2019) Energy minimization in the STT-RAM-based high-capacity last-level caches. J Supercomput 75(10):6831–6854. https://doi.org/10.1007/s11227-019-02918-2

    Article  Google Scholar 

  5. Guo X, Bojnordi MN, Guo Q, Ipek E (2017) Sanitizer: mitigating the impact of expensive ecc checks on stt-mram based main memories. IEEE Trans Comput 67(6):847–860. https://doi.org/10.1109/TC.2017.2779151

    Article  MathSciNet  Google Scholar 

  6. Sayed N, Ebrahimi M, Bishnoi R, Tahoori MB (2017) Opportunistic write for fast and reliable STT-MRAM. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 554–559. Doi: https://doi.org/10.23919/DATE.2017.7927049

  7. Fong X, Kim Y, Choday SH, Roy K (2013) Failure mitigation techniques for 1T–1MTJ spin-transfer torque MRAM bit-cells. IEEE Trans Very Large Scale Integr Syst 22(2):384–395. https://doi.org/10.1109/TVLSI.2013.2239671

    Article  Google Scholar 

  8. Cheshmikhani E, Monazzah AMH, Farbeh H, Miremadi SG (2016) Investigating the effects of process variations and system workloads on reliability of STT-RAM caches. In: Proceedings of the 12th European Dependable Computing Conference (EDCC), pp 120–129. Doi: https://doi.org/10.1109/EDCC.2016.10

  9. Pajouhi Z, Fong X, Raghunathan A, Roy K (2017) Yield, area, and energy optimization in STT-MRAMs using failure-aware ECC. ACM J Emerg Technol Comput Syst (JETC) 13(2):20–39. https://doi.org/10.1145/2934685

    Article  Google Scholar 

  10. Sayed N, Oboril F, Bishnoi R, Tahoori MB (2017) Leveraging systematic unidirectional error-detecting codes for fast STT-MRAM cache. In: Proceedings of the 35th VLSI Test Symposium (VTS), pp 1–6. Doi: https://doi.org/10.1109/VTS.2017.7928937

  11. Aliagha E, Monazzah AMH, Farbeh H (2019) REACT: read/write error rate aware coding technique for emerging STT-MRAM caches. IEEE Trans Magn 55(5):1–8. https://doi.org/10.1109/TMAG.2019.2905523

    Article  Google Scholar 

  12. Takemura R, Kawahara T, Ono K, Miura K, Matsuoka H, Ohno H (2010) Highly-scalable disruptive reading scheme for Gb-scale SPRAM and beyond. In: Proceedings of the IEEE International Memory Workshop, pp 1–2. Doi: https://doi.org/10.1109/IMW.2010.5488324

  13. Wang S, Duan G, Li Y, Dong Q (2017) Word-and partition-level write variation reduction for improving non-volatile cache lifetime. ACM Trans Des Autom Electron Syst (TODAES) 23(1):1–18. https://doi.org/10.1145/3084690

    Article  Google Scholar 

  14. Sun Z, Bi X, Li H, Wong W.F, Ong Z.L, Zhu X, Wu W (2011) Multi retention level STT-RAM cache designs with a dynamic refresh scheme. In: Proceedings of the 44th annual IEEE/ACM International Symposium on Microarchitecture, pp 329–338. Doi: https://doi.org/10.1145/2155620.2155659

  15. Lakys Y, Zhao WS, Devolder T, Zhang Y, Klein JO, Ravelosona D, Chappert C (2012) Self-enabled “error-free” switching circuit for spin transfer torque MRAM and logic. IEEE Trans Magn 48(9):2403–2406. https://doi.org/10.1109/TMAG.2012.2194790

    Article  Google Scholar 

  16. Sethuraman S, Tavva VK, Srinivas M (2021) Techniques to improve write and retention reliability of STT-MRAM memory subsystem. IEEE Trans Comput Aided Des Integr Circuits Syst. https://doi.org/10.1109/TCAD.2021.3118210

    Article  Google Scholar 

  17. Sethuraman S, Tavva VK, Rajamani K, Subramanian CK, Kim K-H, Hunter HC et al (2020) Temperature aware adaptations for improved read reliability in STT-MRAM memory subsystem. IEEE Trans Comput Aided Des Integr Circuits Syst 39(12):4635–4644. https://doi.org/10.1109/TCAD.2020.2982134

    Article  Google Scholar 

  18. Binkert N (2011) The gem5 simulator. ACM SIGARCH Comput Archit News 39(2):1–7. https://doi.org/10.1145/2024716.2024718

    Article  Google Scholar 

  19. Dong X, Xu C, Xie Y, Jouppi NP (2012) Nvsim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans Comput-Aided Des Integr Circuits Syst 31(7):994–1007. https://doi.org/10.1109/TCAD.2012.2185930

    Article  Google Scholar 

  20. Bienia C (2011) Benchmarking modern multiprocessors. Princeton University, Computer Science Dept. Engineering Quadrangle Princeton, NJ, United States. ISBN:978-1-124-49186-8

  21. Wang DT (2005) Modern dram memory systems: performance analysis and scheduling algorithm. Dissertation, University of Maryland

  22. Liu J, Jaiyen B, Veras R, Mutlu O (2012) RAIDR: retention-aware intelligent DRAM refresh. ACM SIGARCH Comput Archit News 40(3):1–12. https://doi.org/10.1145/2366231.2337161

    Article  Google Scholar 

  23. Wang J, Dong X, Xie Y (2014) Enabling high-performance LPDDRx-compatible MRAM. In: Proceedings of the International Symposium on Low Power Electronics and Design, pp 339–344. Doi: https://doi.org/10.1145/2627369.2627610

  24. Kultursay E, Kandemir M, Sivasubramaniam A, Mutlu O (2013) Evaluating STT-RAM as an energy-efficient main memory alternative. In: Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), pp 256–267. Doi: https://doi.org/10.1109/ISPASS.2013.6557176

  25. Meza J, Li J, Mutlu O (2012) A case for small row bufers in non-volatile main memories. In: Proceedings of the 30th International Conference on Computer Design (ICCD), pp 484–485. Doi: https://doi.org/10.1109/iccd.2012.6378685

  26. Zhang Y, Feng D, Tong W, Hua Y, Liu J, Tan Z, Wang C, Wu B, Li Z, Xu G (2018) CACF: a novel circuit architecture co-optimization framework for improving performance, reliability and energy of ReRAM-based main memory system. ACM Trans Archit Code Optim (TACO) 15(2):1–26. https://doi.org/10.1145/3195799

    Article  Google Scholar 

  27. Liu HK, Chen D, Jin H, Liao XF, He B, Hu K, Zhang Y (2021) A survey of non-volatile main memory technologies: state-of-the-arts, practices, and future directions. J Comput Sci Technol 36(1):4–32. https://doi.org/10.1007/s11390-020-0780-z

    Article  Google Scholar 

  28. Asifuzzaman K, Verdejo R, Radojkovivić P (2021) Performance and power estimation of STT-MRAM main memory with reliable system-level simulation. ACM Trans Embed Comput Syst. https://doi.org/10.1145/3476838

    Article  Google Scholar 

  29. Cheshmikhani E, Farbeh H, Asadi H (2019) A system-level framework for analytical and empirical reliability exploration of STT-MRAM caches. IEEE Trans Reliab 69(2):594–610. https://doi.org/10.1109/TR.2019.2923258

    Article  Google Scholar 

  30. Ikeda S, Sato H, Yamanouchi M, Gan H, Miura K, Mizunuma K, Kanai S, Fukami S, Matsukura F, Kasai N (2012) Recent progress of perpendicular anisotropy magnetic tunnel junctions for nonvolatile VLSI. Spin 2(03):1240003. https://doi.org/10.1142/S2010324712400036

    Article  Google Scholar 

  31. Farbeh H, Kim H, Miremadi SG, Kim S (2016) Floating-ECC: Dynamic repositioning of error correcting code bits for extending the lifetime of STT-RAM caches. IEEE Trans Comput 65(12):3661–3675. https://doi.org/10.1109/TC.2016.2557326

    Article  MathSciNet  MATH  Google Scholar 

  32. Farbeh H, Monazzah AMH, Aliagha E, Cheshmikhani E (2018) A-cache: alternating cache allocation to conduct higher endurance in nvm-based caches. IEEE Trans Circuits Syst 66(7):1237–1241. https://doi.org/10.1109/TCSII.2018.2881175

    Article  Google Scholar 

  33. Kim N, Choi K (2016) Exploration of trade-offs in the design of volatile STT–RAM cache. J Syst Archit 71:23–31. https://doi.org/10.1016/j.sysarc.2016.06.005

    Article  Google Scholar 

  34. Kaushik BK, Verma S, Kulkarni AA, Prajapati S (2017) Next generation spin torque memories. Springer, Singapore

    Book  Google Scholar 

  35. Jiang L, Wen W, Wang D, Duan L (2016) Improving read performance of stt-mram based main memories through smash read and flexible read. In: Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp 31–36. Doi: https://doi.org/10.1109/ASPDAC.2016.7427985

  36. Cheshmikhani E, Farbeh H, Asadi H (2019) Enhancing reliability of STT-MRAM caches by eliminating read disturbance accumulation. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 854–859. Doi: https://doi.org/10.23919/DATE.2019.8714946

  37. Nair SM, Bishnoi R, Tahoori MB (2020) Mitigating read failures in STT-MRAM. In: 2020 IEEE 38th VLSI Test Symposium (VTS). Doi: https://doi.org/10.1109/VTS48691.2020.9107605

  38. Zhao W, Zhang Y, Devolder T, Klein JO, Ravelosona D, Chappert C, Mazoyer P (2012) Failure and reliability analysis of STT-MRAM. Microelectron Reliab 52(9–10):1848–1852. https://doi.org/10.1016/j.microrel.2012.06.035

    Article  Google Scholar 

  39. Azad Z, Farbeh H, Monazzah AMH, Miremadi SG (2016) An efficient protection technique for last level STT-RAM caches in multi-core processors. IEEE Tran Parallel Distrib Syst 28(6):1564–1577. https://doi.org/10.1109/TPDS.2016.2628742

    Article  Google Scholar 

  40. Azad Z, Farbeh H, Monazzah A, Miremadi S (2017) AWARE: adaptive way allocation for reconfigurable ECCs to protect write errors in STT-RAM caches. IEEE Trans Emerg Top Comput 7(3):481–492. https://doi.org/10.1109/TETC.2017.2701880

    Article  Google Scholar 

  41. Standard Performance Evaluation Corporation. SPEC CPU2006. https://www.spec.org/cpu2006/

  42. Micron Technology, Inc (2007). https://www.micron.com/media/client/global/documents/ products / technical-note/dram/tn41_01ddr3_power.pdf

  43. Everspin Technologies, (2018). https:// www.mouser.in/datasheet/2/144/EMD3D256MxxBS1_datasheet_v1.0_020918-1313772.pdf

  44. Aziz A, Gupta SK (2016) Hybrid multiplexing (HYM) for read-and area-optimized MRAMs with separate read-write paths. IEEE Trans Nanotechnol 15(3):473–483. https://doi.org/10.1109/TNANO.2016.2544860

    Article  Google Scholar 

  45. Zhao W, Devolder T, Lakys Y, Klein JO, Chappert C, Mazoyer P (2011) Design considerations and strategies for high-reliable STT-MRAM. Microelectron Reliab 51(9–11):1454–1458. https://doi.org/10.1016/j.microrel.2011.07.001

    Article  Google Scholar 

  46. Emre Y, Yang C, Sutaria K, Cao Y, Chakrabarti C (2012) Enhancing the reliability of STT-RAM through circuit and system level techniques. In: Proceedings of the IEEE Workshop on Signal Processing Systems, pp 125–130. Doi: https://doi.org/10.1109/SiPS.2012.11

  47. Im IY, Park SG (2018) A read-write circuit for STT-MRAM with stochastic switchings. IEEE Trans Magn 54(5):1–7. https://doi.org/10.1109/TMAG.2018.2795542

    Article  Google Scholar 

  48. Ghasempour M, Jaleel A, Garside JD, Lujan M (2016) Happy: hybrid address-based page policy in drams. In: Proceedings of the Second International Symposium on Memory Systems, pp 311–321. Doi https://doi.org/10.1145/2989081.2989101

  49. Wang R, Jiang L, Zhang Y, Wang L, Yang J (2015) Selective restore: an energy efficient read disturbance mitigation scheme for future STT-MRAM. In: Proceedings of the 52nd Annual Design Automation Conference (DAC), pp 1–6. Doi: https://doi.org/10.1145/2744769.2744908

  50. Imani M, Rahimi A, Kim Y, Rosing T (2016) A low-power hybrid magnetic cache architecture exploiting narrow-width values. In: Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA), pp 1–6. Doi: https://doi.org/10.1109/NVMSA.2016.7547174

  51. Safayenikoo P, Asad A, Fathy M, Mohammadi F (2017) Exploiting non-uniformity of write accesses for designing a high-endurance hybrid last level cache in 3D CMPs. In: Proceedings of the 30th Canadian Conference on Electrical and Computer Engineering (CCECE), pp 1–5. Doi: https://doi.org/10.1109/CCECE.2017.7946727

  52. Tan Y, Wang B, Yan Z, Deng Q, Chen X, Liu D (2019) UIMigrate: adaptive data migration for hybrid non-volatile memory systems. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 860–865. Doi: https://doi.org/10.23919/DATE.2019.8715118

  53. Gupta Y, Bhargava L (2019) Write energy reduction of STT-MRAM based multi-core cache hierarchies. Int J Electron Lett 7(3):249–261. https://doi.org/10.1080/21681724.2018.1482005

    Article  Google Scholar 

  54. Monazzah AMH, Farbeh H, Miremadi SG (2016) LER: least-error-rate replacement algorithm for emerging STT-RAM caches. IEEE Trans Device Mater Reliab 16(2):220–226. https://doi.org/10.1109/TDMR.2016.2562021

    Article  Google Scholar 

  55. Cheshmikhani E, Farbeh H, Miremadi SG, Asadi H (2018) TA-LRW: a replacement policy for error rate reduction in STT-MRAM caches. IEEE Trans Comput 68(3):455–470. https://doi.org/10.1109/TC.2018.2875439

    Article  MathSciNet  MATH  Google Scholar 

  56. Hadizadeh M, Cheshmikhani E, Asadi H (2020) STAIR: High reliable STT-MRAM aware multi-level I/O cache architecture by adaptive ECC allocation. In: 2020 Design, Automation \& Test in Europe Conference \& Exhibition (DATE). Doi: https://doi.org/10.23919/DATE48585.2020.9116550

  57. Monazzah AM, Rahmani AM, Miele A, Dutt N (2020) CAST: content-aware STT-MRAM cache write management for different levels of approximation. IEEE Trans Comput Aided Des Integr Circuits Syst 39(12):4385–4398. https://doi.org/10.1109/TCAD.2020.2986320

    Article  Google Scholar 

  58. Mittal S (2019) Mitigating read disturbance errors in STT-RAM caches by using data compression. Elsevier Nanoelectronics, pp 133–152. https://doi.org/10.1016/B978-0-12-813353-8.00001-4

  59. Azad Z, Farbeh H, Monazzah AMH (2018) Orient: organized interleaved eccs for new stt-mram caches. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 1187–1190. https://doi.org/10.23919/DATE.2018.8342194

  60. Cheshmikhani E, Farbeh H, Asadi H (2019) ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 173–178. Doi: https://doi.org/10.1145/3287624.3287686

  61. Garzón E, De Rose R, Crupi F, Teman A, Lanuzza M (2021) Exploiting STT-MRAMs for cryogenic non-volatile cache applications. IEEE Trans Nanotechnol 20:123–128. https://doi.org/10.1109/TNANO.2021.3049694

    Article  Google Scholar 

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  1. Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran

    Nooshin Mahdavi & Farhad Razaghian

  2. Department of Computer Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran

    Hamed Farbeh

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  1. Nooshin Mahdavi
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Mahdavi, N., Razaghian, F. & Farbeh, H. Data block manipulation for error rate reduction in STT-MRAM based main memory. J Supercomput 78, 13342–13372 (2022). https://doi.org/10.1007/s11227-022-04394-7

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