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A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms

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Abstract

The Elliptic curve cryptosystem is a public-key cryptosystem that receives more focus in recent years due to its higher security with smaller key size when compared to RSA. Smartcards and other applications have highlighted the importance of security in resource-constrained situations. To meet the increasing need for speed in today’s applications, hardware acceleration with cryptographic algorithms is required. In this paper, we present a novel parallel architecture for elliptic curve scalar multiplication based on a modified Lopez-Dahab–Montgomery(LDM) algorithm, to reduce the total time delay for computing scalar multiplication. It comprises three main steps: affine to projective conversion, point addition and doubling in the main loop followed by reconversion to affine coordinate. The modified parallel algorithm with new inversion in the reconversion yields lesser clock cycle and total time delay compared to existing techniques in the literature for the National Institute of Standards and Technology recommended trinomial \(GF(2^{233})\) . Our proposed architecture implemented on Virtex4 and Virtex7 FPGA technologies, respectively, achieved a lesser clock cycle of 956, which yields a lesser delay of 20.025 and 8.22 μs. Compared with the state-of-the-art of existing techniques, two multiplications are reduced in the reconstruction process and our processor yields 18.29% and 27.21% increase in area-time performance in Virtex 4 and Virtex 7 devices, respectively.

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Abbreviations

ECC:

Elliptic curve cryptography

BEC:

Binary edward curve

ECSM:

Elliptic curve scalar multiplication

GF:

Galois field

FF:

Finite field

PA:

Point addition

PDPoint:

Doubling

ITA:

Itoh-Tsujii inversion algorithm

HITA:

Hex Itoh-Tsujii inversion Algorithm

LUT:

Look-up table

FPGA:

Field programable gate array

CC:

Clock cycle

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Tiruparankundram, Madurai, Tamil Nadu, 625015, India

    M. Kalaiarasi, V. R. Venkatasubramani, V. Vinoth Thyagarajan & S. Rajaram

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  1. M. Kalaiarasi
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  2. V. R. Venkatasubramani
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  3. V. Vinoth Thyagarajan
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  4. S. Rajaram
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Correspondence to M. Kalaiarasi.

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Kalaiarasi, M., Venkatasubramani, V.R., Vinoth Thyagarajan, V. et al. A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms. J Supercomput 78, 15567–15597 (2022). https://doi.org/10.1007/s11227-022-04442-2

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