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A 3-disjoint path design of non-blocking shuffle exchange network by extra port alignment

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Abstract

Multistage Interconnection Networks (MINs) are designed to provide efficient communication via switching. These kinds of MINs are available for large-scale parallel processing. One of such kinds of MINs is Shuffle-Exchange Network (SEN), which facilitates a high level of data transmission with a number of processors working together. Designing this SEN architecture requires a different kind of switching and has wide applications in different kinds of interconnection networks such as omega, cube and binary. Previously, many topologies such as Arrayed Waveguide Gratings and tuneable Wavelength Converters have been presented, but these methods faced low reliability and fewer path possibilities. In these topologies, the connections were made backtracking and non-blocking. These connections are found to be low reliability and with improper control structures. In order to overcome these issues in the design, this paper proposed an enhanced SEN architecture using crossbar switches with five input and output ports that enabled overall path possibilities, thus improving network reliability. Path connections were done using shuffle exchange connections and permutations over source tags that are fault-tolerant. Similarly, a routing table has been implemented to optimise path selection and make the system non-blocking with less switch failure. A tag-based routing has been enabled to generate this routing table, and these tag bits are control lines of the path. There remain three disjoint paths in this routing. Routing has been done using these tags and implemented in enhanced SEN architecture, and the performance has been analysed.

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References

  1. Stergiou E (2020) A study of multistage interconnection networks operating with wormhole routing and equipped with multi-lane storage. Int J Parallel, Emerg Distrib Syst 36(3):1–19

    MathSciNet  Google Scholar 

  2. Prakash A, Yadav DK, Choubey A (2020) Terminal reliability analysis of multistage interconnection networks. Int J Syst Assur Eng Manag 11(1):110–125

    Article  Google Scholar 

  3. Rad F, Reshadi M, Khademzadeh A (2020) A novel arbitration mechanism for crossbar switch in wireless network-on-chip. Cluster Computing, pp 1–14

    Google Scholar 

  4. Amodu OA, Othman M, Yunus NAM, Hanapi ZM (2021) A primer on design aspects and recent advances in shuffle exchange multistage interconnection networks. Symmetry 13(3):378

    Article  Google Scholar 

  5. Amodu OA, Othman M, Nur Arzilawati M, Yunus ZM, Hanapi (2021) A primer on design aspects and recent advances in shuffle exchange multistage interconnection networks. Symmetry 13(3):378. https://doi.org/10.3390/sym13030378

    Article  Google Scholar 

  6. Xiao C, Lou H, Li C, Jin K (2020) August) DBM: A Dimension-Bubble-Based Multicast Routing Algorithm for 2D Mesh Network-on-Chips. Conference on Advanced Computer Architecture. Springer, Singapore, pp 43–55

    Chapter  Google Scholar 

  7. Dadheech P, Kumar A (2020) Fault-tolerant adaptive XY routing for multiprocessors in HPC network. Azerb J High Perform Comput 3(1):94–118. https://doi.org/10.32010/26166127.2020.3.1.94.118

    Article  Google Scholar 

  8. Prasanth NN, Devi KV, Kartheeban K and Manjula V (2020) Crossbar switch scheduling algorithms for high performance computing: A comprehensive review. Materials Today: Proceedings.

  9. Goyal NK, Rajkumar S (2020) Interconnection Network Reliability Evaluation: Multistage Layouts. Wiley

    Book  Google Scholar 

  10. Tabada L and Tagle P (2009) Reliability analysis of a fault tolerant switch. In: Proceedings of International Conference on Computer Engineering and Applications, pp 295–300

  11. Renzini F, Cuppini M, Mucci C, Scarselli EF, Canegallo R (2019) Quantitative analysis of multistage switching networks for embedded programmable devices. Electronics 8(3):272

    Article  Google Scholar 

  12. Webber M, Herbert S, Weidt S, Hensinger WK (2020) Efficient qubit routing for a globally connected trapped ion quantum computer. Adv Quant Technol 3(8):2000027

    Article  Google Scholar 

  13. Yang XP, Song TT, Ye YC, Liu BC, Yan H, Zhu YC, Zheng YL, Liu Y, Xie YY (2020) A novel algorithm for routing paths selection in mesh-based optical networks-on-chips. Micromachines 11(11):996

    Article  Google Scholar 

  14. Habibian H, Patooghy A (2017) Fault-tolerant routing methodology for hypercube and cube-connected cycles interconnection networks. J Supercomput 73(10):4560–4579

    Article  Google Scholar 

  15. Dai Y, Lu K, Xiao L, Su J (2018) A cost-efficient router architecture for HPC inter-connection networks: design and implementation. IEEE Trans Parallel Distrib Syst 30(4):738–753

    Article  Google Scholar 

  16. Alatwi AM, Rashed ANZ, Ahmed M, Amiri IS (2020) Best candidate routing algorithms integrated with minimum processing time and low blocking probability for modern parallel computing systems. Indones J Electr Eng Comput Sci 19:847–854

    Article  Google Scholar 

  17. Bossard A, Kaneko K (2020) Cluster-Fault Tolerant Routing in a Torus. Sensors 20(11):3286

    Article  Google Scholar 

  18. Mnejja S, Aydi Y, Abid M, Monteleon S, Catania V, Palesi M, Patti D (2020) Delta multistage interconnection networks for scalable wireless on-chip communication. Electronics 9(6):913

    Article  Google Scholar 

  19. Abedini R, Ravanmehr R (2020) Parallel SEN: a new approach to improve the reliability of shuffle-exchange network. J Supercomput 76(12):1–35

    Article  Google Scholar 

  20. Xu Q, Chen S, Geng H, Yuan B, Yu B, Wu F, Huang Z (2020) Fault tolerance in memristive crossbar-based neuromorphic computing systems. Integration 70:70–79

    Article  Google Scholar 

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Correspondence to Vipin Sharma.

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Ansari, A.Q., Sharma, V. & Mishra, R. A 3-disjoint path design of non-blocking shuffle exchange network by extra port alignment. J Supercomput 78, 14381–14401 (2022). https://doi.org/10.1007/s11227-022-04450-2

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