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Novel ternary adders and subtractors in quantum cellular automata

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Abstract

In the modern era, advances in CMOS technology have increased the number of transistors and the complexity of computations that can be performed on each chip. Due to the many limitations of this technology, to reduce the size of the chips to the nanotechnology level and to continue Moore’s law, the unique properties of quantum cellular automata have made it a candidate for future integrated circuits. Operational units such as logic and arithmetic units are the main components of processors, among which the operation of addition and subtraction is the most widely used arithmetic operator, and the design of redundant ternary adder without publishing the carry affects the performance of processors. The main aim of this paper is to design a redundant full adder and full subtractor by employing a carry and borrow bit generator module based on ternary QCA (TQCA) innovation. Based on this, the block diagram structure of the ternary redundant adder/subtractor-based TQCA circuit is presented, which includes a proposed new carry/borrow generator gate based on TQCA. The proposed full adder design has 423 ternary cells, area 0.09 µm2 and cost 647.19, and the full subtractor has 431 ternary cells, area 0.09 µm2 and cost 710.7. For validation, the circuits were simulated with the TQCAsim software. The results of this innovation show that the proposed architecture has significant advantages.

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Authors and Affiliations

  1. Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran

    Seyed Mahdi Ghadamgahi & Reza Sabbaghi-Nadooshan

  2. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), P. O. Box 19395-5746, Tehran, Iran

    Reza Sabbaghi-Nadooshan

  3. Department of Electrical Engineering and Computer Science, University of California, Irvine, USA

    Keivan Navi

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Ghadamgahi, S.M., Sabbaghi-Nadooshan, R. & Navi, K. Novel ternary adders and subtractors in quantum cellular automata. J Supercomput 78, 18454–18496 (2022). https://doi.org/10.1007/s11227-022-04593-2

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