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On design and performance analysis of improved shuffle exchange gamma interconnection network layouts

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A Publisher Correction to this article was published on 12 December 2022

A Publisher Correction to this article was published on 07 October 2022

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Abstract

Multistage Interconnection Networks (MINs) are an effective means of communication between multiple processors and memory modules in many parallel processing systems. Literature consists of numerous fault-tolerant MIN designs. However, due to the recent advances in the field of parallel processing, requiring large processing power, an increase in the demand to design and develop more reliable, cost-effective and fault-tolerant MINs is being observed. This work proposes two novel MIN designs, namely, Augmented-Shuffle Exchange Gamma Interconnection Network (A-SEGIN) and Enhanced A-SEGIN (EA-SEGIN). The proposed MINs utilize chaining of switches, and multiplexers & demultiplexers for providing a large number of alternative paths and thereby better fault tolerance. Different reliability measures, namely, 2-terminal, multi-source multi-destination, broadcast and network/global, respectively, of the proposed MINs have been evaluated with the help of all enumerated paths and well-known Sum-of-Disjoint Products approach. Further, overall performance, with respect to the number of paths, different reliability measures, hardware cost and cost per unit, of the proposed MINs has been compared with 19 other well-studied MIN layouts. The results suggest that the proposed MINs are very strong competitors of the preexisting MINs of their class owing to their better reliability and cost effectiveness.

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Acknowledgements

The authors would like to thank the editor and anonymous reviewers whose valued comments helped to improve the readability and quality of this paper.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India

    Gaurav Khanna

  2. Subir Chowdhury School of Quality and Reliability, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India

    Sanjay K. Chaturvedi

  3. Department of Communication Technology and Network, Universiti Putra Malaysia (UPM), 43400, Serdang, Selangor D.E, Malaysia

    Mohamed Othman

  4. Laboratory of Computational Sciences and Mathematical Physics, Institute for Mathematical Research, Universiti Putra Malaysia (UPM), 43400, Serdang, Selangor D.E, Malaysia

    Mohamed Othman

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  1. Gaurav Khanna
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The original online version of this article was revised: A correction has been made for clearer presentation of the formula under Expression in Table 7.

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Khanna, G., Chaturvedi, S.K. & Othman, M. On design and performance analysis of improved shuffle exchange gamma interconnection network layouts. J Supercomput 79, 11611–11640 (2023). https://doi.org/10.1007/s11227-022-04735-6

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