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Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata

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Abstract

A quantum-dot cellular automaton is a new technology that solves all the disputes CMOS technology faces. Quantum-dot cellular automata-based computations run at ultra-high speeds with very high device density and low power consumption. Reversible logic design, featured in quantum-dot cellular automata, permits fully invertible computation. The arithmetic and logic units are the major components in all microprocessor-based systems that probably serve as the processing device's heart. This paper discusses an area-efficient quantum-dot cellular automata technology-based coplanar, reversible arithmetic and logic unit using the double Peres and Feynman gates. With a latency of \(2.5\) clocks and a total area of 0.1 μm2, the proposed arithmetic and logic unit performs 19 logic and arithmetic operations. QCA Designer and QD-E are used to simulate the proposed design and energy consumption, respectively. The proposed design's total energy dissipation, as measured by QCA Designer-E, is 5.45e−002 eV, and the average energy dissipation is 4.95e−003 eV. The proposed method has a considerable number of improvements in terms of latency, the number of operations, and area compared to earlier work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India

    Rama Krishna Reddy Venna & G. Durga Jayakumar

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  1. Rama Krishna Reddy Venna
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  2. G. Durga Jayakumar
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Contributions

Rama Krishna Reddy Venna and G. Durga Jayakumar were both involved in the study’s conception. Rama Krishna Reddy Venna was in charge of material preparation, data gathering, design, and analysis. Rama Krishna Reddy Venna wrote the first draft of the manuscript, and both writers commented on prior versions of the manuscript before signing off on the final version.

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Correspondence to Rama Krishna Reddy Venna.

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Venna, R.K.R., Jayakumar, G.D. Design of novel area-efficient coplanar reversible arithmetic and logic unit with an energy estimation in quantum-dot cellular automata. J Supercomput 79, 1908–1925 (2023). https://doi.org/10.1007/s11227-022-04740-9

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