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Parallel SHA-256 on SW26010 many-core processor for hashing of multiple messages

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Abstract

To explore whether new parallelism techniques can provide additional performance improvements in cryptographic hash functions, we conducted our study with the SW26010, which is a special-architecture processor on Sunway TaihuLight, one of the world’s fastest supercomputers. Secure Hash Algorithms (SHAs) are significant for secure transmission, with SHA-256 remaining a safe and most efficient SHA design. We propose SW-SHA-256, a parallel SHA-256 implementation for hashing of multiple messages on the SW26010. Our work explores the parallel schemes at the instruction and thread levels. At the instruction level, we use vector registers to load multiple messages to complete hashing simultaneously. Assembly-level optimization methods such as dual issue are used, and the pipeline is distinct from that of a general-purpose processor. At the thread level, the optimized DMA transmission strategy and double buffer technique are used to reduce the cost from memory to cache. As a result, we obtain 5.87 cycles per byte in a single core which is 8.18X speed up faster than the C code in OpenSSLv3.0.0. Moreover, our implementation achieves a throughput of 60.21 GB/s on a SW26010 processor and is highly scalable.

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The data used to support the findings of this study are available from the corresponding author upon request.

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Acknowledgements

This research has been supported by the China National Key R &D Program (Grant No. 2018YFB1700405).

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Authors and Affiliations

  1. School of Computer Science and Technology, Xi’an Jiaotong University, West Xianning Road, Xi’an, 710049, Shaanxi, China

    Ziheng Wang, Xiaoshe Dong, Yan Kang & Heng Chen

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  1. Ziheng Wang
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Correspondence to Heng Chen.

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Wang, Z., Dong, X., Kang, Y. et al. Parallel SHA-256 on SW26010 many-core processor for hashing of multiple messages. J Supercomput 79, 2332–2355 (2023). https://doi.org/10.1007/s11227-022-04750-7

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