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Logic Realization of Galois Field for AES SBOX using Quantum Dot Cellular Automata

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Abstract

With the growing technological trends in VLSI domain, quantum dot cellular automata (QCA) technology is slowly replacing CMOS technology due to its smaller feature size, high operating frequency and reduced power consumption. In the initial research phase, QCA has been used to implement various combinatorial and sequential circuits models, which are the fundamental blocks in various applications. Nowadays, researchers focus on the implementation of application-based designs using QCA. This motivated to implement the Galois field (GF) functions for SBox module in the most secure cryptography encryption standard AES with QCA. In AES, SBOX is the predominant power consumption modules. Hence, a research has been carried out to implement a compact QCA-based AES-SBOX with GF. This paper describes the implementation of our proposed QCA-based AES-SBOX with Galois field and analysis of various GF functional modules in terms of area, performance, energy and QCA cells used. The functional verification is performed using the simulated waveforms.

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The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

References

  1. Sen B, Nag A, De A, Sikdar BK (2015) Towards the hierarchical design of multilayer QCA logic circuit. J Comput Sci 11:233–244. https://doi.org/10.1016/j.jocs.2015.09.010

    Article  Google Scholar 

  2. Singhal R (2000) “Logic Realization Using Regular Structures in Quantum-Dot Cellular Automata (QCA),” Jan. https://doi.org/10.15760/etd.196

  3. Wilson M, Kannangara K, Smith G, Simmons M, Raguse B (2002) Nanotechnology: basic science and emerging technologies. CRC Press

    Book  Google Scholar 

  4. Organizing DESCHALL, in Brute Force, New York, NY: Springer New York (2005), pp. 63–73. https://doi.org/10.1007/0-387-27160-0_9

  5. Laajimi R, Niu M (2018) “Nanoarchitecture of Quantum-Dot Cellular Automata (QCA) Using Small Area for Digital Circuits,” Advanced Electronics Circuits–Principles, Architectures and Applications on Emerging Technologies, pp. 67–84

  6. Bahar AN, Waheed S, Hossain N, Asaduzzaman M (2018) A novel 3-input XOR function implementation in quantum dot-cellular automata with energy dissipation analysis. Alexandria Eng J 57(2):729–738

    Article  Google Scholar 

  7. Navi K, Farazkish R, Sayedsalehi S, Azghadi MR (2010) A new quantum-dot cellular automata full-adder. Microelectron J 41(12):820–826

    Article  Google Scholar 

  8. Angizi S, Alkaldy E, Bagherzadeh N, Navi K (2014) Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. J Low Power Electron 10(2):259–271

    Article  Google Scholar 

  9. Hashemi S, Rahimi Azghadi M, Navi K (2019) Design and analysis of efficient QCA reversible adders. J Supercomput 75(4):2106–2125. https://doi.org/10.1007/s11227-018-2683-0

    Article  Google Scholar 

  10. Khan A, Arya R (Jan. 2022) Design and energy dissipation analysis of simple QCA multiplexer for nanocomputing. J Supercomput. https://doi.org/10.1007/s11227-021-04191-8

  11. Khan A, Arya R (2021) Optimal demultiplexer unit design and energy estimation using quantum dot cellular automata. J Supercomput 77(2):1714–1738. https://doi.org/10.1007/s11227-020-03320-z

    Article  Google Scholar 

  12. Oskouei SM, Ghaffari A (2019) Designing a new reversible ALU by QCA for reducing occupation area. J Supercomput 75(8):5118–5144. https://doi.org/10.1007/s11227-019-02788-8

    Article  Google Scholar 

  13. Kianpour M, Sabbaghi-Nadooshan R, Navi K (2014) A novel design of 8-bit adder/subtractor by quantum-dot cellular automata. J Comput Syst Sci 80(7):1404–1414. https://doi.org/10.1016/j.jcss.2014.04.012

    Article  MathSciNet  MATH  Google Scholar 

  14. Amiri MA, Mirzakuchaki S, Mahdavi M, Department EE (2010) “LOGIC-BASED QCA IMPLEMENTATION OF A \(4\times 4\) S-BOX,” p. 7

  15. Mahdavi M, Amiri MA (2018) High Level Modeling of AES in QCA Technology. Majlesi Journal of Telecommunication Devices 7(4)

  16. Lent CS, Tougaw PD, Porod W, Bernstein GH (1993) Quantum cellular automata. Nanotechnology 4(1):49

    Article  Google Scholar 

  17. Kim K, Wu K, Karri R (2006) The robust QCA adder designs using composable QCA building blocks. IEEE trans comput aided des integr circuits sys 26(1):176–183

    Article  Google Scholar 

  18. Sasamal TN, Singh AK, Mohan A (2020) Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective, vol 879. Springer Singapore, Singapore. https://doi.org/10.1007/978-981-15-1823-2

    Book  MATH  Google Scholar 

  19. Majeed AH, Zainal MSB, Alkaldy E, Nor DM (2020) Full Adder Circuit Design with Novel Lower Complexity XOR Gate in QCA Technology. Trans Electr Electron Mater 21(2):198–207. https://doi.org/10.1007/s42341-019-00166-y

    Article  Google Scholar 

  20. Wang L, Xie G (2020) A Novel XOR/XNOR Structure for Modular Design of QCA Circuits. IEEE Trans Circuits Syst II 67(12):3327–3331. https://doi.org/10.1109/TCSII.2020.2989496

    Article  Google Scholar 

  21. Roohi A, Zand R, Angizi S, DeMara RF (2018) A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency. IEEE Trans Emerg Topics Comput 6(4):450–459. https://doi.org/10.1109/TETC.2016.2593634

    Article  Google Scholar 

  22. Khan A, Mandal S (2019) Robust multiplexer design and analysis using quantum dot cellular automata. Int J Theoretical Phys 58(3):719–733

    Article  MathSciNet  MATH  Google Scholar 

  23. Pub NF (2001) 197: Advanced encryption standard (AES). Federal inf proces stand publ 197(441):0311

    Google Scholar 

  24. P R, H M (Jan. 2021) Design and implementation of power and area optimized AES architecture on FPGA for IoT application. Circuit World 47(2):153–163. https://doi.org/10.1108/CW-04-2019-0039

  25. Rajasekar P, Mangalam H (2016) Design of Low Power Optimized MixColumn/Inverse MixColumn Architecture for AES. Int J Appl Eng Res 11(2):922–926

    Google Scholar 

  26. Rajasekar P, Mangalam H (2015) Design and implementation of low power multistage AES S box. Int J Appl Eng Res 10:40535–40540

    Google Scholar 

  27. Satoh A, Morioka S, Takano K, Munetoh S (2001) “A compact Rijndael hardware architecture with S-box optimization.” In: International Conference on the Theory and Application of Cryptology and Information Security, pp. 239–254

  28. Järvinen KU, Tommiska MT, Skyttä JO (2003) “A fully pipelined memoryless 17.8 Gbps AES-128 encryptor.” In: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, pp. 207–215

  29. Satoh A, Morioka S, Takano K, Munetoh S (2001) “A compact Rijndael hardware architecture with S-box optimization.” In: International Conference on the Theory and Application of Cryptology and Information Security, pp. 239–254

  30. Rashidi B, Rashidi B (2013) Implementation of an optimized and pipelined combinational logic rijndael S-Box on FPGA. International Journal of Computer Network & Information Security 5(1)

  31. Walus K, Dysart TJ, Jullien GA, Budiman RA (2004) QCADesigner: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata. IEEE Trans Nanotechnol 3(1):26–31. https://doi.org/10.1109/TNANO.2003.820815

    Article  Google Scholar 

  32. Sill Torres F, Wille R, Niemann P, Drechsler R (2018) An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. IEEE Trans Comput Aided Des Integr Circuits Syst 37(12):3031–3041. https://doi.org/10.1109/TCAD.2018.2789782

    Article  Google Scholar 

  33. Khan A, Arya R (Jul. 2019) “Energy Dissipation and Cell Displacement Analysis of QCA Multiplexer for Nanocomputation.” In: 2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), Chennai, India, pp. 1–5. https://doi.org/10.1109/ICESIP46348.2019.8938359

  34. Kalaiselvi K, Mangalam H (2015) Power efficient and high performance VLSI architecture for AES algorithm. J Electrical Sys Inf Technol 2(2):178–183. https://doi.org/10.1016/j.jesit.2015.04.002

    Article  Google Scholar 

  35. Rijmen V (2000) Efficient Implementation of the Rijndael S-box. Katholieke Universiteit Leuven, Dept, ESAT. Belgium

    Google Scholar 

  36. Srivastava S, Sarkar S, Bhanja S (2008) Estimation of upper bound of power dissipation in QCA circuits. IEEE trans nanotechnol 8(1):116–127

    Article  Google Scholar 

  37. Liu W, Srivastava S, Lu L, O’Neill M, Swartzlander EE (2012) Are QCA cryptographic circuits resistant to power analysis attack? IEEE trans nanotechnol 11(6):1239–1251

    Article  Google Scholar 

  38. Das JC, De D (2012, December) Quantum dot-cellular automata based cipher text design for nano-communication. In 2012 International Conference on Radar, Communication and Computing (ICRCC) (pp. 224-229). IEEE

  39. Amiri MA, Mirzakuchaki A, Mahdavi M (2011) A5/1 implementation in quantum cellular automata. Nanosci Nanotechnol 1(2):58–63

    Article  Google Scholar 

  40. Debnath B, Das JC, De D (2019) Nanoscale cryptographic architecture design using quantum-dot cellular automata. Front Inf Technol Electronic Eng 20(11):1578–1586. https://doi.org/10.1631/FITEE.1800458

    Article  Google Scholar 

  41. Debnath B et al (2020) Security analysis with novel image masking based quantum-dot cellular automata nformation security model. IEEE Access 8:117159–117172. https://doi.org/10.1109/ACCESS.2020.3002081

    Article  Google Scholar 

  42. Kundu A, Chandra Das J, De D (2022) RSCV: Reversible select, cross and variation architecture in quantum-dot cellular automata. IET Quant Comm 3(2):139–149. https://doi.org/10.1049/qtc2.12040

    Article  Google Scholar 

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Rajasekar, P., Mangalam, H. & Kumar, C.S.S. Logic Realization of Galois Field for AES SBOX using Quantum Dot Cellular Automata. J Supercomput 79, 3024–3054 (2023). https://doi.org/10.1007/s11227-022-04779-8

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