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Efficient tasks scheduling in multicore systems integrated with hardware accelerators

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Abstract

Multicore systems integrated with hardware accelerators provide better performance for executing real-time applications in time-critical fields, such as robots, avionics, and aerospace. The integration of hardware accelerators brings new challenges for system scheduling; the software scheduling problem is extended to a hardware–software co-scheduling problem. Efficient co-scheduling strategy maximizes the benefits of hardware acceleration, which is important for time-critical systems. To solve this problem, we propose a co-scheduling strategy to minimize the system execution time. It combines hardware–software resource allocation and a real-time schedule method. Our scheduling can fit the different parallel in software and hardware (e.g., CPUs and FPGAs). The key component of our strategy is its novel hardware–software resource allocation and a high-performance heuristic scheduling algorithm. In the experiments, we evaluate our approach using both simulated and real parallel applications. The results illustrate that our algorithm obtains efficient solutions within reasonable runtimes compared to the state of the art.

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Data availability

The datasets generated during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

The authors would like to thank the editors and anonymous reviewers for their constructive comments. The authors would like to thank Professor Patrice Quinton from Inria, Rennes, France, for his valuable suggestions. Thanks for the supports from him and the Inria team TARAN. This work was also supported in part by the National Key Research and Development Project of China (2018YFB2101300), the Dean’s Fund of Engineering Research Center of Software/Hardware Co-design Technology and Application, Ministry of Education (East China Normal University), Shanghai Collaborative Innovation Center for Trusted Industrial Internet Software, and Shanghai Trusted Industry Internet Software Collaborative Innovation Center.

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Authors and Affiliations

  1. Software Engineering Institute, East China Normal University, No. 3663, North Zhongshan Road, Shanghai, 20062, China

    Jinyi Xu, Hao Shi & Yixiang Chen

  2. Taran, IRISA INRIA, 35000, Rennes, France

    Jinyi Xu

  3. MOE Engineering Research Center for Software/Hardware Co-Design Technology and Application, East China Normal University, No. 3663, North Zhongshan Road, Shanghai, 20062, China

    Jinyi Xu, Hao Shi & Yixiang Chen

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  1. Jinyi Xu
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Xu, J., Shi, H. & Chen, Y. Efficient tasks scheduling in multicore systems integrated with hardware accelerators. J Supercomput 79, 7244–7271 (2023). https://doi.org/10.1007/s11227-022-04955-w

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