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An ultra-area-efficient ALU design in QCA technology using synchronized clock zone scheme

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Abstract

A quantum-dot cellular automaton (QCA) is currently regarded as a radical nanotechnology that is rapidly growing and offering new methods for achieving high-speed computing at the nano-scale. It is an advanced transistor-less nanotechnology, considered for ultra-low-power dissipation, high functioning speed in THz, high device density, and less circuit complexity as a replacement for CMOS technology. This work demonstrates a new circuit design and implementation of the single-bit arithmetic logic unit (ALU) in QCA technology. This can be reduced in terms of the number of quantum cell count, reduced latency, minimization of the design area, optimization of the power consumption and calculation of the effects of temperature on output cell at temperature range 1–7 K by using novel QCADesigner-E (Energy) Version 2.2 tool. The presented ALU design is constructed by 18 × 18 nm QCA cell size, using coherence vector simulation engine setup parameters to provide a regular synchronized clock zone. The proposed design has achieved an improvement of 46.15% of the overall design area, 36.36% of the QCA cell area, and 25.00% of the delay by using the multilayer crossover technique. The proposed design of the QCA–ALU layout and functional verification of the design is performed by using the QCADesigner-E.

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Acknowledgements

We wish to thank the anonymous referees for their valuable comments and suggestions that contributed to improving the quality of the work in this paper.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Indore Institute of Science and Technology, Indore, Madhya Pradesh, 452001, India

    Mukesh Patidar

  2. Department of Information Technology, Shri Govindram Seksaria Institute of Technology and Science, Indore, Madhya Pradesh, 452001, India

    Upendra Singh

  3. Department of Computer Science & Engineering, Graphic Era Deemed to Be University, Dehradun, Uttarakhand, 248002, India

    Surendra Kumar Shukla

  4. Department of Electronics and Communication Engineering, Sree Chaitanya Institute of Technological Science, Karimnagar, Telengana, 505527, India

    Giriraj Kumar Prajapati

  5. Department of Electronics Engineering, Shri Vaishnav Institute of Technology and Science, Indore, Madhya Pradesh, 452001, India

    Namit Gupta

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  1. Mukesh Patidar
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  4. Giriraj Kumar Prajapati
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Contributions

Authors M Patidar, U Singh, and GK Prajapati wrote the main manuscript text, Authors M Patidar, SK Shukla, and N Gupta prepared figures and table, Authors M Patidar and N Gupta design the layout and verified the results, Authors M Patidar, U Singh, SK Shukla and GK Prajapati cross-check the results. All authors reviewed the manuscript.

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Correspondence to Mukesh Patidar.

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Patidar, M., Singh, U., Shukla, S.K. et al. An ultra-area-efficient ALU design in QCA technology using synchronized clock zone scheme. J Supercomput 79, 8265–8294 (2023). https://doi.org/10.1007/s11227-022-05012-2

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