Abstract
True random number generator (TRNG) is built on hardware-based non-deterministic noise for generating keys, initialization vectors, and random numbers, and it plays an important role in various applications that require encryption protection. In this paper, a true random number generator based on MUX unit multiphase sampling is proposed by investigating the frequency jitter mechanism. The scheme is based on the “soft macro” design of the MUX unit, which replaces the traditional look-up table entropy scheme. It completes high-precision jitter sampling on the basis of ensuring the fairness of the TRNG entropy source and can be well transplanted to a series of FPGAs. The proposed TRNG is verified on three FPGAs of Xilinx Virtex-6, Artix-7, and Virtex-7. The experimental results show that the generated random sequences are of good quality, passing the NIST SP800-22 tests with higher p-value and NIST SP 800-90B tests with higher minimum entropy, while achieving 100 Mbps throughput. It is worth mentioning that the resource overhead consumed by the proposed TRNG is small and unitary, only consuming 4 MUX units, 5 DFFs, and 1 LUT unit, which has a good application prospect.
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All data generated or analyzed during this study are available from the corresponding author on reasonable request.
References
Jeong Y-S, Oh K-J, Cho C-K, Choi H-J (2020) Pseudo-random number generation using LSTMs. J Supercomput 76:8324–8342. https://doi.org/10.1007/s11227-020-03229-7
Chen TY, Ma Y, Lin JQ, Cao Y, Lv N, Jing JW (2021) A lightweight full entropy trng with on-chip entropy assurance. IEEE Trans Comput Aided Des Integr Circuits Syst 40:2431–2444. https://doi.org/10.1109/tcad.2021.3096464
Poudel B, Munir A (2018) Design and evaluation of a PVT variation-resistant TRNG circuit. In: 2018 IEEE 36th international conference on computer design (ICCD), pp 514–521. doi:https://doi.org/10.1109/iccd.2018.00083
Ma Y, Chen T, Lin J, Yang J, Jing J (2019) Entropy estimation for ADC sampling-based true random number generators. IEEE Trans Inf Forensics Secur 14:2887–2900. https://doi.org/10.1109/tifs.2019.2908798
Xu X, Liang H, Zhou K, Ma G, Huang Z, Yi M, Ni T, Lu Y (2018) An all-digital and jitter-quantizing true random number generator in SRAM-based FPGAs. In: 2018 IEEE 27th Asian test symposium (ATS), pp 59–62. doi:https://doi.org/10.1109/ats.2018.00022
Mei F, Zhang L, Gu C, Cao Y, Wang C, Liu W (2018) A highly flexible lightweight and high speed true random number generator on FPGA. In: 2018 IEEE computer society annual symposium on VLSI (ISVLSI), pp 399–404. doi:https://doi.org/10.1109/isvlsi.2018.00079
Ma G, Liang H, Yao L, Huang Z, Yi M, Xu X, Zhou K (2018) A low-cost high-efficiency true random number generator on FPGAs. In: 2018 IEEE 27th Asian test symposium (ATS), 54–58. doi:https://doi.org/10.1109/ats.2018.00021
Lu Y, Liang H, Yao L, Wang X, Qi H, Yi M, Jiang C, Huang Z (2020) Jitter-quantizing-based TRNG robust against PVT variations. IEEE Access 8:108482–108490. https://doi.org/10.1109/access.2020.3000231
Della Sala R, Bellizia D, Scotti G (2022) A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators. IEEE Trans Circuits and Syst II Express Briefs 69:1672–1676. https://doi.org/10.1109/tcsii.2021.3121537
Tuna M, Karthikeyan A, Rajagopal K, Alcin M, Koyuncu İ (2019) Hyperjerk multiscroll oscillators with megastability: analysis, FPGA implementation and a novel ANN-ring-based true random number generator. AEU Int J Electron Commun 112:152941. https://doi.org/10.1016/j.aeue.2019.152941
Wang X, Liang H, Wang Y, Yao L, Guo Y, Yi M, Huang Z, Qi H, Lu Y (2021) High-throughput portable true random number generator based on jitter-latch structure. IEEE Trans Circuits Syst I Regul Pap 68:741–750. https://doi.org/10.1109/TCSI.2020.3037173
Meitei HB, Kumar M (2022) FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter. SN Appl Sci 4:96. https://doi.org/10.1007/s42452-022-04981-6
Li X, Shen L, Zhao Z (2012) Jitter test of multiphase DTTL. Phys Procedia 25:623–629. https://doi.org/10.1016/j.phpro.2012.03.135
Cornaglia B, Spini M (1995) SDH in digital satellite systems. In: Proceedings of the tenth international conference on digital satellite communications
Xilinx Corporation. (2016). 7 Series FPGAs Configurable Logic Block [EB/OL]. [Online]. Available: https://docs.xilinx.com/v/u/en-US/ug474_7Series_CLB
Yao L, Liang H, Han Q, Zhang H, Huang Z, Jiang C, Yi M, Lu Y (2022) M-RO PUF: a portable pure digital RO PUF based on MUX unit. Microelectron J 119:105314. https://doi.org/10.1016/j.mejo.2021.105314
Wold K, Petrović S (2011) Behavioral model of TRNG based on oscillator rings implemented in FPGA. In: Proceedings of the 14th IEEE international symposium on design and diagnostics of electronic circuits and systems, 13–15 April 2011, pp 163–166
Valtchanov B, Aubert A, Bernard F, Fischer V (2008) Modeling and observing the jitter in ring oscillators implemented in FPGAs. In: Proceedings of the 2008 11th IEEE workshop on design and diagnostics of electronic circuits and systems, 16–18 April 2008, pp 1–6
Xilinx Corporation. (2012). Virtex-6 FPGA Configurable Logic Block (UG364). [EB/OL]. [Online] https://www.xilinx.com/support/documentation/user_guides/ug364pdf
Barker E, Kelsey J, Secretary JB (2012) NIST DRAFT special publication 800–90B recommendation for the entropy sources used for random bit generation. NIST special publication
Rukhin A, Soto J, Nechvatal J, Smid M, Barker E (2001) A statistical test suite for random and pseudorandom number generators for cryptographic applications. Nist special publication
Cui J, Yi M, Cao D, Yao L, Wang X, Liang H, Huang Z, Qi H, Ni T, Lu Y (2022) Design of true random number generator based on multi-stage feedback ring oscillator. IEEE Trans Circuits Syst II Express Briefs 69:1752–1756. https://doi.org/10.1109/TCSII.2021.3111049
Barker E, Kelsey J (2012) Recommendation for the entropy sources used for random bit generation. Draft NIST special publication
Martin H, Martin-Holgado P, Peris-Lopez P, Morilla Y, Entrena L (2018) On the entropy of oscillator-based true random number generators under ionizing radiation. Entropy 20:513
Nalla Anandakumar N, Sanadhya SK, Hashmi MS (2020) FPGA-based true random number generation using programmable delays in oscillator-rings. IEEE Trans Circuits Syst II Express Briefs 67:570–574. https://doi.org/10.1109/tcsii.2019.2919891
Funding
This work is supported by the Major National Scientific Instrument and Equipment Development Project under Grant No. 62027815; the National Natural Science Foundation of China under Grant No. 61674048; and the Science and Technology on Electronic Test and Measurement Laboratory of China under Grant No. 61420010202717.
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L.Y. and H.L. helped in conceptualization; L.Y. helped in methodology; H.L. and L.Y. helped in validation; L.Y. helped in writing—original draft preparation; Y.L. helped in writing—review and editing; H.L. worked in supervision; and H.L. worked in project administration.
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Yao, L., Liang, H. & Lu, Y. Low-overhead TRNG based on MUX for cryptographic protection using multiphase sampling. J Supercomput 79, 17170–17186 (2023). https://doi.org/10.1007/s11227-023-05349-2
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DOI: https://doi.org/10.1007/s11227-023-05349-2