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Scalable short-entry dual-grain coherence directories with flexible region granularity

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Abstract

As the number of cores in a chip multiprocessor increase, the directory size becomes excessive. Current research shows that directory size can be reduced by tracking private entries with coarse-grain directory entries called region entries. In order to indicate which blocks the region owner has cached, the present vector in the region entries in the dual-grain directory (DGD) uses a bit vector format. If a coarser-grain region granularity is used, the length of the region entries becomes excessive. Besides, most of the latest scalable directories use the short-entry directory format with only one pointer. Therefore, DGD has limited flexibility of region granularity and is incompatible with the latest scalable directories. In this paper, we propose a scalable short-entry dual-grain coherence directory with flexible region granularity (SS-DGD). In private region entries, a counter is used instead of the original bit vector. Region entries using counters and private block entries using a single pointer always have the same length, giving SS-DGD the flexibility of region size. To reduce the directory size, SS-DGD is divided into a shared directory and a private directory that includes private block entries and private region entries. With the same total number of directory entries, SS-DGD has a smaller directory size than previous DGD because the private directory entries in SS-DGD are shorter. And the detailed simulation-based study shows that there are no statistically significant differences in execution time and network traffic between SS-DGD and DGD. In the 64-core system, our proposal can reduce the directory size by 29.9%. More importantly, the region entries in SS-DGD can be used in the latest scalable directories and have a high potential to compress the number of directory entries.

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Data availability

The datasets used or analysed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work was supported in part by the National Natural Science Foundation of China under Grant 62031009, in part by Alibaba Innovative Research (AIR) Program, in part by the Fudan University-CIOMP Joint Fund(FC2019-001), in part by the Fudan-ZTE Joint Lab, in part by Pioneering Project of Academy for Engineering and Technology Fudan University(gyy2021-001), in part by CCF-Alibaba Innovative Research Fund For Young Scholars.

Funding

This work was supported in part by the National Natural Science Foundation of China under Grant 62031009, in part by Alibaba Innovative Research (AIR) Program, in part by the Fudan University-CIOMP Joint Fund(FC2019-001), in part by the Fudan-ZTE Joint Lab, in part by Pioneering Project of Academy for Engineering and Technology Fudan University(gyy2021-001), in part by CCF-Alibaba Innovative Research Fund For Young Scholars.

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Authors and Affiliations

  1. State Key Laboratory of ASIC and System Department of Microelectronics, Fudan University, Shanghai, China

    Yuxin Tang, Yudi Qiu, Yanwei Liu, Jie Jiao & Yibo Fan

  2. Advanced Institute of Information Technology, Peking University, Beijing, China

    Peng Zhang

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  1. Yuxin Tang
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Y and Y wrote the main manuscript text. All authors helped with the experiments and reviewed the manuscript.

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Correspondence to Yibo Fan.

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Tang, Y., Qiu, Y., Liu, Y. et al. Scalable short-entry dual-grain coherence directories with flexible region granularity. J Supercomput 80, 2889–2911 (2024). https://doi.org/10.1007/s11227-023-05559-8

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