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Dedicated hardware design for efficient quantum computations using classical logic gates

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Abstract

This work presents a novel approach to quantum computing by proposing a customizable hardware design of a dedicated processor that emulates the execution of quantum algorithms. Unlike software-based quantum computation simulators, which run on standard general-purpose computers and suffer from reduced performance, this hardware design, which is based on classical concepts of bits, registers and memories, aims to leverage pure parallelism and pipelined execution for efficient quantum computations via emulation. The architecture includes several key components: memories, computation unit, measurement unit and control unit. The quantum state memory stores the individual and group states of qubits. This memory is crucial for maintaining the quantum information required for quantum operations. Basic operators are stored in dedicated operator memory. Additionally, a scratch memory allows for larger operators to be dynamically built at runtime. The computation unit is responsible for performing complex number multiplications, which form the basis of tensor and matrix products necessary for executing quantum operations. A measurement unit enables quantum state sampling, which is an essential aspect of quantum computation. Furthermore, a control unit is incorporated to ensure the correct operation of the quantum processor’s data path. It utilizes a microprogram to manage and coordinate the functional units. All the functional units communicate with each other through dedicated and shared data buses, depending on the frequency of information exchange. This enables efficient data transfer and coordination among the components. The proposed hardware design has been simulated and proved to be effective in executing quantum operations. By exploiting parallelism and employing a pipelined execution, this architecture overcomes the limitations of software-based simulators, delivering improved performance for emulating quantum algorithms. We use Grover’s search algorithm as a benchmark to evaluate the performance of the proposed hardware design and compare it to software-based simulation and to hardware-based algorithm-dedicated emulation.

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Notes

  1. Note that there are other unary, binary and ternary as well as multi-qubit operators not mentioned here.

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Acknowledgements

The authors are grateful to the reviewers whose comments, recommendations and suggestions improved enormously the contents of this manuscript.

Funding

This research work received funding from FAPERJ: Fundação Carlos Chagas Filho de Amparo à Pesquisa do Estado do Rio de Janeiro (https://www.faperj.br/) in Brazil: Grant No. 201.013/2022.

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Authors and Affiliations

  1. Department of Electronics Engineering and Telecommunications, Engineering Faculty, State University of Rio de Janeiro, Rio de Janeiro, Brazil

    Nadia Nedjah

  2. Post-Graduate Program of Electronics Engineering, Engineering Faculty, State University of Rio de Janeiro, Rio de Janeiro, Brazil

    Sérgio Raposo

  3. Department of Systems Engineering and Computation, Engineering Faculty, State University of Rio de Janeiro, Rio de Janeiro, Brazil

    Luiza de Macedo Mourelle

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  1. Nadia Nedjah
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  2. Sérgio Raposo
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  3. Luiza de Macedo Mourelle
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NN and LM validated the design and wrote the manuscript; and SR implemented the design

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Correspondence to Nadia Nedjah.

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Nedjah, N., Raposo, S. & de Macedo Mourelle, L. Dedicated hardware design for efficient quantum computations using classical logic gates. J Supercomput 80, 7028–7070 (2024). https://doi.org/10.1007/s11227-023-05687-1

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