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Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks

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Abstract

On-chip networks (NoCs) have become a popular choice for designing large multiprocessor architectures. Software-based emulation is often used to perform the design verification. However, if the considered design is sufficiently large, software-based emulation becomes impractically slow. To avoid this limitation, multi-FPGA emulation was introduced, where multiple interconnected FPGAs collectively emulate a single circuit. The number of external FPGA pins is often insufficient for emulating large network-on-chip designs accurately. As a result, the overall emulation frequency has to be severely limited. We propose a method for accelerating multi-FPGA emulation by reducing the amount of data FPGAs need to transmit to each other. To achieve cycle-accurate emulation in the absence of constant transmission latency, synchronous messaging is implemented. The proposed method was tested on a functioning prototype. It is shown that the use of our method for multi-FPGA emulation of large NoC designs can reach several orders.

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Data availability

The software associated with this article is freely available at https://github.com/alerner-6502/NoC_partitioner/

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Funding

This article is an output of a research project implemented as part of the Basic Research Program at the National Research University Higher School of Economics (HSE University).

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  1. HSE University, 34 Tallinskaya Ulitsa, Moscow, Russian Federation, 123458

    Aleksandr Y. Romanov, Anatoly Lerner & Aleksandr A. Amerikanov

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  1. Aleksandr Y. Romanov
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Contributions

Conceptualization was done by A.Y.R., A.L., and A.A.A.; methodology was done by A.Y.R.; validation was done by A.Y.R. and A.L.; writing—original draft preparation was done by A.Y.R. and A.L.; writing—review and editing was done by A.A.A. All authors have read and agreed to the published version of the manuscript.

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Correspondence to Aleksandr Y. Romanov.

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Romanov, A.Y., Lerner, A. & Amerikanov, A.A. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks. J Supercomput 80, 22462–22478 (2024). https://doi.org/10.1007/s11227-024-06306-3

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