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Subgraph matching-based reference placement for printed circuit board designs

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Abstract

Reference placement is promising to handle the increasing complexity in printed circuit board (PCB) designs, which aims to find the isomorphism of the placed template in component combination to reuse the placement. In this paper, we convert the netlist information into a graph and then model the reference placement as a subgraph matching problem. Since the state-of-the-art subgraph matching methods usually recursively search the solutions and suffer from high time and memory consumption in large-scale designs, we develop a novel subgraph matching algorithm D2BS with diversity tolerance and improved backtracking to guarantee matching quality and efficiency. The D2BS algorithm is founded on a data structure called the candidate space (CS) structure. We build and filter the candidate set for each query node according to our designed features to construct the CS structure. During the CS optimization process, a graph diversity tolerance strategy is adopted to achieve efficient inexact matching. Then, hierarchical matching is developed to search the template embeddings in the CS structure guided by branch backtracking and matched-node snatching strategies. Based on the industrial PCB designs, experimental results show that D2BS outperforms the state-of-the-art subgraph matching method in matching accuracy and running time.

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No datasets were generated or analyzed during the current study.

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Acknowledgements

This work was partially supported by the National Natural Science Foundation of China under Grants 62104037 and 92373207 and the MOST of Taiwan under Grant MOST 110-2221-E-002-177-MY3.

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Authors and Affiliations

  1. National ASIC System Engineering Center, Southeast University, Nanjing, 210096, China

    Ziran Zhu & Yilin Li

  2. College of Mathematics and Computer Science, Fuzhou University, Fuzhou, 350108, China

    Miaodi Su, Shu Zhang & Haiyuan Su

  3. Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA

    Yifeng Xiao

  4. Hangzhou Huawei Enterprises Telecommunication Technologies Co., Ltd, Hangzhou, 310000, China

    Huan He

  5. State Key Lab of ASIC and System, Fudan University, Shanghai, 200433, China

    Jianli Chen

  6. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 10617, Taiwan

    Yao-Wen Chang

  7. Department of Electrical Engineering, National Taiwan University, Taipei, 10617, Taiwan

    Yao-Wen Chang

Authors
  1. Ziran Zhu
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  2. Yilin Li
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  3. Miaodi Su
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  4. Shu Zhang
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  8. Jianli Chen
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  9. Yao-Wen Chang
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Contributions

ZZ, YL, and MS gave the idea and wrote the main manuscript text. YL, MS, HS, and YX did the experiments. All authors reviewed the manuscript.

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Correspondence to Ziran Zhu.

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Preliminary version of this paper was presented at the 2022 ACM/IEEE Design Automation Conference (DAC’22), San Francisco, CA, USA, July 2022 [1].

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Zhu, Z., Li, Y., Su, M. et al. Subgraph matching-based reference placement for printed circuit board designs. J Supercomput 80, 24324–24357 (2024). https://doi.org/10.1007/s11227-024-06338-9

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