Abstract
The present era has witnessed the wide deployment of reconfigurable hardware or Field Programmable Gate Arrays (FPGAs) in edge and cloud platforms. With its ability of dynamic partial reconfiguration at runtime, FPGAs provide the apt environment to execute a variety of real-time tasks in strict power and timing constraints. However, threats associated with the vulnerability of hardware like hardware Trojan horses may cause sudden delays at runtime or may even drain the power budget of the system to prevent completion of the tasks before their associated deadlines. We consider a resource-constraint FPGA-based edge platform with strict power budget. This is associated with execution of several periodic and nonperiodic hard real-time approximate computing tasks, i.e., tasks whose result can vary within a certain range but must complete within a prespecified deadline. We depict how delay inducing and power draining hardware Trojans may jeopardize the scenario. We propose deployment of low overhead agents or self-aware modules (SAMs) that can facilitate decentralized control and nonintrusive security in such an environment. With each FPGA that is entrusted with execution of a series of tasks or a task schedule, a SAM is associated. The SAM continuously monitors the performance of its host, based on prespecified power and timing data. On detecting any anomaly, it outsources the tasks to other SAMs for execution in other FPGAs, so that the tasks can complete their execution prior to their deadline. Low resource utilization and timing overhead of SAM, high task success rate for periodic tasks and low task rejection rate for nonperiodic tasks depict the suitability of our proposed mechanism.
























Similar content being viewed by others
Availability of data and materials
Datasets used are confidential, till publication, and then will be published in an open forum, along with codes.
References
Liu Y, Peng M, Shou G, Chen Y, Chen S (2020) Toward edge intelligence: multiaccess edge computing for 5g and internet of things. IEEE Internet Thing J 7(8):6722–6747
Wei T, Zhou J, Cao K, Cong P, Chen M, Zhang G, Hu XS, Yan J (2017) Cost-constrained QoS optimization for approximate computation real-time tasks in heterogeneous MPSoCs. IEEE Trans Comput-Aided Des Integr Circuit Syst 37(9):1733–1746
Minhas UI, Woods R, Nikolopoulos DS, Karakonstantis G (2021) Efficient, dynamic multi-task execution on FPGA-based computing systems. IEEE Trans Parallel Distrib Syst 33(3):710–722
Mal-Sarkar S, Karam R, Narasimhan S, Ghosh A, Krishna A, Bhunia S (2016) Design and validation for FPGA trust under hardware trojan attacks. IEEE Trans Multi-Scale Comput Syst 2(3):186–198
Chakraborty RS, Saha I, Palchaudhuri A, Naik GK (2013) Hardware trojan insertion by direct modification of FPGA configuration bitstream. IEEE Des Test 30(2):45–54
Bhunia S, Hsiao MS, Banga M, Narasimhan S (2014) Hardware trojan attacks: threat analysis and countermeasures. Proc IEEE 102(8):1229–1247
Chakraborty RS, Wolff F, Paul S, Papachristou C, Bhunia S (2009) Mero: A statistical approach for hardware trojan detection. In: International Workshop on Cryptographic Hardware and Embedded Systems, pp. 396–410 . Springer.
Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S (2012) Hardware trojan detection by multiple-parameter side-channel analysis. IEEE Trans Comput 62(11):2183–2195
Herder C, Yu M-D, Koushanfar F, Devadas S (2014) Physical unclonable functions and applications: a tutorial. Proc IEEE 102(8):1126–1141
Saha D, Sur-Kolay S (2014) Watermarking in hard intellectual property for pre-fab and post-fab verification. IEEE Trans Very Large Scale Integr (VLSI) Syst 23(5):801–809
Chakraborty RS, Bhunia S (2009) Harpoon: an obfuscation-based soc design methodology for hardware protection. IEEE Trans Comput-Aided Des Integr Circuit Syst 28(10):1493–1502
Guha, K., Saha, D., Chakrabarti, A.: Self aware soc security to counteract delay inducing hardware trojans at runtime. In: 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pp. 417–422 (2017). IEEE
Amazon E (2009) Amazon elastic compute cloud. Retrieved Feb 10
Caulfield AM, Chung ES, Putnam A, Angepat H, Fowers J, Haselman M, Heil S, Humphrey M, Kaur P, Kim J-Y, et al.: A cloud-scale acceleration architecture. In: 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 1–13 (2016). IEEE
Saha S, Sarkar A, Chakrabarti A (2017) Spatio-temporal scheduling of preemptive real-time tasks on partially reconfigurable systems. ACM Trans Des Autom Electron Syst(TODAES) 22(4):1–26
Guha K, Saha S, Chakrabarti A (2018) Shirt (self healing intelligent real time) scheduling for secure embedded task processing. In: 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 463–464 . IEEE Computer Society
Kohútka L, Stopjaková V (2020) Novel efficient on-chip task scheduler for multi-core hard real-time systems. Microprocess Microsyst 76:103083
Kohútka L (2022) Scheduling periodic real-time tasks with inter-task synchronisation. In: 2022 11th Mediterranean Conference on Embedded Computing (MECO), pp. 1–4
Kohútka L (2022) A new FPGA-based architecture of task scheduler with support of periodic real-time tasks. In: 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), pp. 77–82
Kohútka L, Stopjaková V (2019) A new hardware-accelerated scheduler for soft real-time tasks. In: 2019 8th Mediterranean Conference on Embedded Computing (MECO), pp. 1–4 . https://doi.org/10.1109/MECO.2019.8760040
Kohútka L, Stopjaková V (2020) ASIC architecture and implementation of red scheduler for mixed-criticality real-time systems. In: 2020 27th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), pp. 83–88
Palumbo A, Cassano L, Luzzi B, Hernández JA, Reviriego P, Bianchi G, Ottavi M (2022) Is your FPGA bitstream hardware trojan-free? Machine learning can provide an answer. J Syst Architect 128:102543. https://doi.org/10.1016/j.sysarc.2022.102543
Chithra C, Kokila J, Ramasubramanian N (2020) Detection of hardware trojans using machine learning in soc fpgas. In: 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), pp. 1–7 . https://doi.org/10.1109/CONECCT50063.2020.9198475
Elnaggar R, Chakrabarty K, Tahoori MB (2019) Hardware trojan detection using changepoint-based anomaly detection techniques. IEEE Trans Very Large Scale Integr (VLSI) Syst 27(12):2706–2719. https://doi.org/10.1109/TVLSI.2019.2925807
Jin C, Gohil V, Karri R, Rajendran J (2020) Security of cloud FPGA: A survey. arXiv preprint arXiv:2005.04867
Liu C, Rajendran J, Yang C, Karri R (2014) Shielding heterogeneous MPSoCs from untrustworthy 3pips through security-driven task scheduling. IEEE Trans Emerg Top Comput 2(4):461–472
Sunkavilli S, Zhang Z, Yu Q (2021) New security threats on FPGAS: From FPGA design tools perspective. In: 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 278–283 . IEEE
Zhang J, Qu G (2019) Recent attacks and defenses on FPGA-based systems. ACM Trans Reconfig Technol Syst (TRETS) 12(3):1–24
Guha K, Saha D, Chakrabarti A (2020) Blockchain technology enabled pay per use licensing approach for hardware ips. In: 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1618–1621 . IEEE
Giechaskiel I, Eguro K, Rasmussen KB (2019) Leakier wires: exploiting FPGA long wires for covert-and side-channel attacks. ACM Trans Reconfig Technol Syst (TRETS) 12(3):1–29
Chen C-Y, Choi J, Gopalakrishnan K, Srinivasan V, Venkataramani S (2018) Exploiting approximate computing for deep learning acceleration. In: 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 821–826 . IEEE
Tan C, Muthukaruppan TS, Mitra T, Ju L (2015) Approximation-aware scheduling on heterogeneous multi-core architectures. In: The 20th Asia and South Pacific Design Automation Conference, pp. 618–623 . IEEE
Saha S, Chakraborty S, Zhai X, Ehsan S, McDonald-Maier KD (2022) Accurate: accuracy maximization for real-time multicore systems with energy-efficient way-sharing caches. IEEE Trans Comput-Aided Des Integr Circuit Syst 41(12):5246–5260
Yu H, Veeravalli B, Ha Y (2008) Dynamic scheduling of imprecise-computation tasks in maximizing qos under energy constraints for embedded systems. In: 2008 Asia and South Pacific Design Automation Conference, pp. 452–455 . IEEE
Stavrinides GL, Karatza HD (2010) Scheduling multiple task graphs with end-to-end deadlines in distributed real-time systems utilizing imprecise computations. J Syst Softw 83(6):1004–1014
Cao K, Xu G, Zhou J, Wei T, Chen M, Hu S (2018) Qos-adaptive approximate real-time computation for mobility-aware IoT lifetime optimization. IEEE Trans Comput-Aided Des Integr Circuit Syst 38(10):1799–1810
Méndez-Díaz I, Orozco J, Santos R, Zabala P (2017) Energy-aware scheduling mandatory/optional tasks in multicore real-time systems. Int Trans Op Res 24(1–2):173–198
Zhou J, Yan J, Wei T, Chen M, Hu XS (2017) Energy-adaptive scheduling of imprecise computation tasks for qos optimization in real-time MPSoC systems. In: Design, Automation Test in Europe Conference Exhibition (DATE), 2017, pp. 1402–1407
Guha K, Saha D, Chakrabarti A(2018) Sarp: self aware runtime protection against integrity attacks of hardware trojans. In: International Symposium on VLSI Design and Test, pp. 198–209 . Springer
Guha K, Saha D, Chakrabarti A (2017) Real-time soc security against passive threats using crypsis behavior of geckos. ACM J Emerg Technol Comput Syst (JETC) 13(3):1–26
Guha K, Saha D, Chakrabarti A (2019) Stigmergy-based security for soc operations from runtime performance degradation of soc components. ACM Trans Embed Comput Syst (TECS) 18(2):1–26
Guha K, Majumder A, Saha D, Chakrabarti A (2019) Criticality based reliability against hardware trojan attacks for processing of tasks on reconfigurable hardware. Microprocess Microsyst 71:102865
Guha K, Saha D, Chakrabarti A (2020) A multi-agent co-operative model to facilitate criticality based reliability for mixed critical task execution on fpga based cloud environment. In: 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), pp. 143–148 . IEEE
Yu S-Y, Yasaei R, Zhou Q, Nguyen T, Faruque MAA (2021) HW2VEC: A graph learning tool for automating hardware security.
Yazdanbakhsh A, Mahajan D, Esmaeilzadeh H, Lotfi-Kamran P (2016) Axbench: a multiplatform benchmark suite for approximate computing. IEEE Des Test 34(2):60–68
Xilinx: Vivado design suite tutorial: partial reconfiguration (UG947). Link: https://docs.amd.com/r/en-US/ug947-vivado-partial-reconfiguration-tutorial (2024)
Shakya B, He T, Salmani H, Forte D, Bhunia S, Tehranipoor M (2017) Benchmarking of hardware trojans and maliciously affected circuits. J Hardw Syst Sec 1:85–102
Salmani H, Tehranipoor M, Karri R (2013) On design vulnerability analysis and trust benchmarks development. In: 2013 IEEE 31st International Conference on Computer Design (ICCD), pp. 471–474 . IEEE
Saha D, Sur-Kolay S (2020) Minimization of WCRT with recovery assurance from hardware trojans for tasks on FPGA-based cloud. ACM Trans Embed Comput Syst. https://doi.org/10.1145/3409479
Guha K, Saha S, McDonald-Maier K (2022) Senas: Security driven energy aware scheduler for real time approximate computing tasks on multi-processor systems. In: 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 1–5 . https://doi.org/10.1109/IOLTS56730.2022.9897811
Author information
Authors and Affiliations
Contributions
Single author, hence, this field is not applicable.
Corresponding author
Ethics declarations
Conflict of interest
The authors declare no competing interests.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Guha, K. Self-aware decentralized security for real time approximate computing tasks in FPGA-based edge platforms. J Supercomput 81, 121 (2025). https://doi.org/10.1007/s11227-024-06538-3
Accepted:
Published:
DOI: https://doi.org/10.1007/s11227-024-06538-3