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FPGA-based architecture and implementation techniques of a low-complexity hybrid RAKE receiver for a DS-UWB communication system

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Abstract

In this paper, the architecture of a low-complexity Direct Sequence Ultra-Wideband (DS-UWB) receiver subsystem which incorporates a Channel Estimator (CE) and a novel hybrid Partial/Selective (HPS) maximal ratio combining (MRC) RAKE receiver is presented. Three different design techniques followed by FPGA implementation are investigated and compared and system performance results are provided. The proposed architectures combine the benefits of both partial and selective RAKE receiver algorithms and the obtained results demonstrate the trade-off between energy capture, performance and receiver complexity. All design approaches focus on a highly parallel, modular and optimized for high performance system which is necessary for demanding and low-cost applications of UWB communications.

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Authors and Affiliations

  1. Applied Electronics Laboratory, Department of Electrical and Computer Engineering, University of Patras, Campus of Rion, Patras, Greece

    Christos Thomos & Grigorios Kalivas

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  1. Christos Thomos
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  2. Grigorios Kalivas
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Correspondence to Christos Thomos.

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Thomos, C., Kalivas, G. FPGA-based architecture and implementation techniques of a low-complexity hybrid RAKE receiver for a DS-UWB communication system. Telecommun Syst 52, 2083–2099 (2013). https://doi.org/10.1007/s11235-011-9487-3

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  • DOI: https://doi.org/10.1007/s11235-011-9487-3

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