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Efficient FPGA implementation of a STBC-OFDM combiner for an IEEE 802.16 software radio receiver

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Abstract

In this paper, an efficient FPGA implementation of a 4×4 Space-Time Block Coding (STBC) combiner for MIMO-OFDM software radio receivers is considered. The proposed combiner is based on a low-complexity algorithm which reduces the interference due to the Quasi-Orthogonality of the STBC decoding. In the literature, feedback techniques have been proposed to solve this problem. However, the algorithm introduced in this paper has been conceived in order to avoid the transmission feedback, by estimating the interference factors and removing them. The proposed algorithm exhibits a low computational complexity and complies with the requirements of HW feasibility, considering the execution time/area occupation trade-off.

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Authors and Affiliations

  1. Department of Electronic Systems, Radio Access Technology Section, Aalborg University, Aalborg, 9220, Denmark

    Andrea F. Cattoni

  2. Department of Electronic Systems, Technology Platforms Section, Aalborg University, Aalborg, 9220, Denmark

    Yannick Le Moullec

  3. Dept. of Information Engineering and Computer Science (DISI), University of Trento, Trento, 38123, Italy

    Claudio Sacchi

Authors
  1. Andrea F. Cattoni
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  2. Yannick Le Moullec
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  3. Claudio Sacchi
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Correspondence to Andrea F. Cattoni.

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Cattoni, A.F., Le Moullec, Y. & Sacchi, C. Efficient FPGA implementation of a STBC-OFDM combiner for an IEEE 802.16 software radio receiver. Telecommun Syst 56, 245–255 (2014). https://doi.org/10.1007/s11235-013-9833-8

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