Skip to main content

Advertisement

Log in

Proposing an optimal structure for the architecture of wireless networks on chip

  • Published:
Telecommunication Systems Aims and scope Submit manuscript

Abstract

The need for more scalability in design on one hand and the occurrence of latency and high power consumption in communications between distant cores on the other hand are considered as the most common challenges which networks on chip encounter. Today, wireless network on chip (WiNoC) is regarded as a novel proposed approach in which wireless links are shortcuts for the fast data transmission between distant cores. However, the presence of Wireless routers (WRs) in WiNoC increases the cost and area. Thus, finding an optimal structure for communicating between cores is essential. In this paper, genetic algorithm (GA) and simulated annealing (SA) are compared with each other under different traffic patterns to find the best positions of WRs. The results obtained from the simulations of this study indicate that GA has higher efficiency than SA. Furthermore, the resulting structure has fewer WRs and relatively desirable performance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24
Fig. 25
Fig. 26
Fig. 27

Similar content being viewed by others

References

  1. Benini, L., & De Micheli, G. (2002). Network on chip: A new paradigm for systems on chip design. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition (pp. 418-419).

  2. ITRS, International Technology Roadmap for Semiconductors (2007).

  3. Shacham, A., Bergman, K., & Carloni, L. (2008). Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Transactions on Computers, 57(9), 1246–1260.

    Article  Google Scholar 

  4. Chang, M., Cong, J., Kaplan, A., Naik, M., Reinman, G., Socher, E., & Tam, S.-W. (2008). CMP network-on-chip overlaid with multi-band RF-interconnect. In Proceedings of IEEE International Symposium High-Performance Computer Architecture (HPCA) (pp. 191–202).

  5. Carloni, L., Pande, P., & Xie, Y. (2009). Network-on-chip in emerging interconnect paradigms: Advantages and challenges. In Proceedings of \(3^{rd}\) ACM/IEEE International Symposium Network-on-Chip (pp. 93–102).

  6. Zhao, D., & Wang, Y. (2008). SD-MAC: Design and Synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Transactions on Computers, 57(9), 1230–1245.

    Article  Google Scholar 

  7. Hu, W.-H., Wang, C., & Bagherzadeh, N. (2012). Design and analysis of a mesh-based wireless network-on-chip. In Proceedings of \(20^{th}\) Euromicro International Parallel, Distributed and Network-Based Processing (PDP) Conference (pp. 483–490).

  8. ARM. ARM11 MPCore. (http://www.arm.com).

  9. IBM. IBM PowerPC405 Embedded Core. (http://www.ibm.com).

  10. Wang, C., Hu, W.-H., & Bagherzadeh, N. (2011). A wireless network-on-chip design for multicore platforms. In Proceedings of \(19^{th}\) Euromicro International Parallel, Distributed and Network-Based Processing (PDP) Conference (pp. 409–416).

  11. Wang, C., Hu, W.-H., & Bagherzadeh, N. (2012). A load-balanced congestion-aware wireless network-on-chip design for multicore platforms. Microprocessor and Microsystems, 36(7), 555–570.

    Article  Google Scholar 

  12. Kirkpatrick, S., Gelatt, C, Jr, Vecchi, M., & McCoy, A. (1983). Optimization by simulated annealing. Science, 220(4598), 671–679.

    Article  Google Scholar 

  13. Holland, J. (1975). Adaptation in natural and artificial systems. Ann Arbor: University of Michigan Press.

    Google Scholar 

  14. Pavlidis, V., & Friedman, E. (2006). 3-D topologies for networks-on-chip. In IEEE International SOC Conference (pp. 285–288).

  15. Pande, P., Ganguly, A., Chang, K., & Teuscher, C. (2009). Hybrid wireless network on chip: A new paradigm in multi-core design. In \(2^{nd}\) International Workshop on Network on Chip Architectures (pp. 71–76).

  16. Deb, S., Ganguly, A., Chang, K., Pande, P., Belzer, B., & Heo, D. (2010). Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects. In the 21st IEEE International Conference on Application-specific Systems Architectures and Processors.

  17. Shacham, A., Bergman, K., & Carloni, L. P. (2007). On the design of a photonic network-on-chip. In Proceedings SNC (pp. 53–64).

  18. Krishnamoorthy, A. V., Ho, R., Zheng, X., et al. (2009). Computer systems based on silicon photonic interconnects. Proceedings of the IEEE, 9(7), 1337–1361.

    Article  Google Scholar 

  19. Gu, H., & Xu. J. (2009). Design of 3D optical network on chip. In Proceedings SOPO (pp. 1–4).

  20. Ye, Y., Xu, J., Huang, B., et al. (2013). 3-D mesh-based optical network-on-chip for multiprocessor system-on-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(4), 584–596.

    Article  Google Scholar 

  21. Cai, Q., Hou, W., & Yu, C. (2014). Design and OPNET implementation of routing algorithm in 3D optical network on chip. In Proceedings IEEE/CIC (pp. 112–115).

  22. Bai, L., Gu, H., Yang, Y., & Wang, K. (2012). A crosstalk aware routing algorithm for Benes ONoC. IEICE Electronics Express, 9(12), 1069–1074.

    Article  Google Scholar 

  23. Hou, W., et al. (2014). 3D torus ONoC: Topology design, router modeling and routing algorithm. Proceeding ICOCN.

  24. Wang, S., & Jin, T. (2014). Wireless network-on-chip: A survey. Journal of Engineering, 1(1), 1–7.

    Article  Google Scholar 

  25. Kim, K., Yoon, H., & O, K. (2000). On-chip wireless interconnection with integrated antennas. In Electron Devices Meeting (pp. 485–488).

  26. Floyd, B., Hung, C.-M., & O, K. (2002). Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE Journal of Solid-State Circuits, 37(5), 543–552.

    Article  Google Scholar 

  27. Zhao, D., Wang, Y., Li, J., & Kikkawa, T. (2011). Design of multi-channel wireless noc to improve on-chip communication capacity. In Fifth ACM/IEEE International Symposium on Network-on-Chip (pp. 177–184).

  28. Tomassini, M., Giacobini, M., & Darabos, C. (2005). Evolution and dynamics of small-world cellular automata. Complex Systems, 15(4), 261–284.

    Google Scholar 

  29. Korte, B., & Vygen, J. (2008). Combinatorial optimization: Theory and algorithms (4th ed.). Berlin: Springer.

    Google Scholar 

  30. Dally, W., & Towles, B. (2003). Principles and practices of interconnection networks (1st ed.). San Francisco: Morgan Kaufmann.

    Google Scholar 

  31. Parhami, B. (2002). Introduction to parallel processing algorithms and architectures. New York: Kluwer Academic Publishers.

    Google Scholar 

  32. El-Rewini, H., & Abd-El-Barr, M. (2005). Advanced computer architecture and parallel processing. New Jersey: Wiley.

    Google Scholar 

  33. Soteriou, V., Eisley, N., Wang, H., Li, B., & Peh, L.-S. (2006). Polaris: A system-level roadmap for on-chip interconnection networks. In International Conference on Computer Design (pp. 134–141).

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Mohammad Ali Jabraeil Jamali.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bahrami, B., Jamali, M.A.J. & Saeidi, S. Proposing an optimal structure for the architecture of wireless networks on chip. Telecommun Syst 62, 199–214 (2016). https://doi.org/10.1007/s11235-015-0075-9

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11235-015-0075-9

Keywords

Navigation