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Design of interfaces between high speed data converters and high performance FPGAs for software defined radio applications

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Abstract

Software defined radio (SDR) is a vast and emerging field that requires the design of various technologies such as antenna, RF, IF, and digital baseband subsystems. Among all these technologies, data converters that convert signals between analog and digital domains are highly crucial. On the other hand field programmable gate arrays (FPGAs) based platforms are being preferred for evaluating and implementing the digital communication concepts due to their programmability and reconfigurability. As a result they are well suited for the design of SDR technology. In this research work, we develop a platform where high-speed data converters are interfaced with high performance FPGAs. Interfaces are designed for analog-to-digital convertors (ADC) and digital-to-analog convertors (DAC) to communicate with FPGAs. For the interface design between ADC and FPGA, a double data rate and a low voltage differential signalling based serial output is adopted. And, for the interface design between DAC and other FPGA, parallel complementary metal oxide semiconductor outputs are used. To reconfigure the modes and parameters of the data convertors, serial peripheral interface data controllers have been designed. We have through simulations evaluated the performance of our designed interfaces between data convertors and FPGAs.

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References

  1. http://www.altera.com.

  2. http://www.xilinx.com.

  3. Alasti, H. (2018). A low complexity and flexible implementation of \(2^{n}\)-QAM for software defined radio applications. In 2018 15th IEEE annual consumer communications networking conference (CCNC) (pp. 1–6).

  4. Cai, X., Zhou, M., & Huang, X. (2017). Model-based design for software defined radio on an FPGA. IEEE Access, 5, 8276–8283.

    Article  Google Scholar 

  5. Cai, X., Zhou, M., & Huang, X. (2017). Model-based design for software defined radio on an FPGA. IEEE Access, 5, 8276–8283.

    Article  Google Scholar 

  6. Cummings, M., & Haruyama, S. (1999). FPGA in the software radio. IEEE Communications Magazine, 37(2), 108–112.

    Article  Google Scholar 

  7. Defossez, M. (2006). Connecting Xilinx FPGAs to Texas Instruments ADS527x series ADCs. Application Note: Virtex-II, Virtex-II Pro, and Spartan-3 Families.

  8. Defossez, M. (2008). An interface for Texas instruments analog-to-digital converters with serial LVDS outputs. Application Note: Virtex-4 and Virtex-5 FPGAs.

  9. Goeller, L., & Tate, D. (2014). A technical review of software defined radios: Vision, reality, and current status. In 2014 IEEE military communications conference (pp. 1466–1470).

  10. Hervás, M., Alsina-Pagès, R. M., & Salvador, M. (2016). An FPGA scalable software defined radio platform design for educational and research purposes. Electronics, 5(2), 27.

    Article  Google Scholar 

  11. Hiari, O., & Mesleh, R. (2017). A reconfigurable SDR transmitter platform architecture for space modulation mimo techniques. IEEE Access, 5, 24214–24228.

    Article  Google Scholar 

  12. Interfacing Analog to Digital Converters to FPGAs. White paper (2007).

  13. Jondral, F. K. (2005). Software-defined radio sbasics and evolution to cognitive radio. Journal on Wireless Communications and Networking, 3, 275–283.

    Google Scholar 

  14. Junior, S. B., de Oliveira, V. C., & Junior, G. B. (2015). Software defined radio implementation of a QPSK modulator/demodulator in an extensive hardware platform based on FPGAs Xilinx ZYNQ. Journal of Computer Science, 11(4), 598–611.

    Article  Google Scholar 

  15. Panda, A. R., Mishra, D., & Ratha, H. K. (2017). FPGA implementation of a tone-based flight termination system in a software-defined radio platform. IEEE Transactions on Industrial Informatics, 13(5), 2360–2368.

    Article  Google Scholar 

  16. Salkintzis, A. K., Nie, H., & Mathiopoulos, P. T. (1999). ADC and DSP challenges in the development of software radio base stations. IEEE Personal Communications, 6(4), 47–55.

    Article  Google Scholar 

  17. Sruthi, M. B., Abirami, M., Manikkoth, A., Gandhiraj, R., & Soman, K. P. (2013). Low cost digital transceiver design for software defined radio using RTL-SDR. In 2013 international mutli-conference on automation, computing, communication, control and compressed sensing (iMac4s) (pp 852–855).

  18. Stewart, R. W., Crockett, L., Atkinson, D., Barlee, K., Crawford, D., Chalmers, I., et al. (2015). A low-cost desktop software defined radio design environment using MATLAB, simulink, and the RTL-SDR. IEEE Communications Magazine, 53(9), 64–71.

    Article  Google Scholar 

  19. Texas Instruments: DAC5687-16-BIT, 500 MSPS 2-8 Interpolating dual-channel digital-to-analog converter (DAC). (2006).

  20. Texas Instruments: DAC5687 EVM user guide. (2007).

  21. Texas Instruments: ADS62P43- DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC with DDR LVDS/CMOS outputs (2009).

  22. Vergari, F. (2013). Software-defined radio: Finding its use in public safety. IEEE Vehicular Technology Magazine, 8(2), 71–82.

    Article  Google Scholar 

  23. Xilinx Inc.: UG331-Spartan-3 Generation FPGA User Guide; Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families. (2009).

  24. Xilinx Inc.: Virtex-5 Libraries Guide for HDL designs. (2009).

  25. Zhang, F., Yang, Z., Feng, W., Cui, H., Huang, L., & Hu, W. (2008). A high speed CMOS transmitter and rail-to-rail receiver. In 4th IEEE International Symposium on Electronic Design, Test and Applications, 2008. DELTA 2008 (pp. 67 –70).

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Correspondence to Khalim Amjad Meerja.

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Balakrishnan, M., Meerja, K.A., Gundugonti, K.K. et al. Design of interfaces between high speed data converters and high performance FPGAs for software defined radio applications. Telecommun Syst 71, 601–614 (2019). https://doi.org/10.1007/s11235-018-00539-3

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  • DOI: https://doi.org/10.1007/s11235-018-00539-3

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