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The design of a configurable and low-latency packet parsing system for communication networks

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Abstract

Parsing is a critical packet processing function in the network node, and the performance and configurability of the packet parsing is essential for designing a low-latency and highly flexible network. This paper presents the VLSI architecture design and circuit implementation of a configurable and low-latency packet parser. The proposed packet parser is based on an instruction architecture to achieve configurability. Furthermore, a novel instruction-reusing scheme is employed in the packet parser so that the instruction-fetch operation is minimized and the latency is reduced. Moreover, in order to reduce size of the required memory, a new structure for the instruction memory is designed where multiple instructions share the same memory location. The proposed packet parser is designed and implemented with a ASIC design flow as well as based on the FPGA platform. Performance evaluations based on the post-layout simulation shows that the proposed packet parser reduces the latency by 30% and the required memory by 70%for the IPv4 and IPv6 protocols.

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References

  1. Mukherjee, A. (2018). Energy efficiency and delay in 5G ultra-reliable low-latency communications system architectures. IEEE Network, 32 (2), 55–61.

  2. Zunxin, Z., Linmei, W., Fumin, Z., Ling, L. (2021). Potential technologies and applications based on deep learning in the 6G networks. Computers & Electrical Engineering, 95.

  3. Xu, D. et al. (2018). A survey of opportunistic offloading. IEEE Communications Surveys & Tutorials, 20 (3), 2198–2236.

  4. Pham, Q., et al. (2020). A survey of multi-access edge computing in 5G and Beyond: fundamentals, technology integration, and state-of-the-art. IEEE Access, 8, 116974–117017.

    Article  Google Scholar 

  5. Chen, M., & Hao, Y. (2018). Task offloading for mobile edge computing in software defined ultra-dense network. IEEE Journal on Selected Areas in Communications, 36(3), 587–597.

    Article  Google Scholar 

  6. Sepehr, A., Mahrokh, A., Mehran, A., Negin, S., & Justin, L. (2021). Performance analysis of multi-hop routing protocols in SDN-based wireless networks. Computers & Electrical Engineering.**

  7. Nazemi, S., Leung, K. K., & Swami, A. (2019). Distributed optimization framework for in-network data processing. IEEE/ACM Transactions on Networking, 27(6), 2432–2443.

    Article  Google Scholar 

  8. Rüth, J. et al. (2018). Demo abstract: Towards in-network processing for low-latency industrial control. IEEE INFOCOM WKSHPS, pp. 1–2.

  9. da Silva, J. S., Boyer, F.-R., & Langlois, J. M. P. (2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs. In: ACM/SIGDA Int. Symp. Field Program. Gate Arrays, pp. 147–152.

  10. Bosshart, P., et al. (2013). Forwarding metamorphosis: Fast programmable match-action processing in hardware for SDN. ACM SIGCOMM Computer Communication Review, 43(4), 99–110.

    Article  Google Scholar 

  11. Pontarelli, S., Bifulco, R., Bonola, M., Cascone, C., Spaziani, M., & Bruschi, V. et al. (2019). FlowBlaze: Stateful packet processing in hardware. In: USENIX Symp. Netw. Syst. Design Implement., pp. 531–548.

  12. Zolfaghari, H., Rossi, D., & Nurmi, J. (2020). A custom processor for protocol-independent packet parsing. Microprocessors and Microsystems, 72.

  13. Zolfaghari, H., Rossi, D., & Nurmi, J.(2018). Low-latency Packet Parsing in Software Defined Networks. In: IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip.

  14. Zolfaghari, H., Rossi, D., & Nurmi, J. (2018). An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks. In: IEEE International Conference on Application-specific Systems, Architectures and Processors, 2018, pp. 1–4.

  15. Yazdinejad, A., Parizi, R. M., Bohlooli, A., Dehghantanha, A., & Raymond Choo, K.-K. (2020). A high-performance framework for a network programmable packet processor using P4 and FPGA. Journal of Network and Computer Applications, 156.

  16. Cabal, J., Benáček, P., Kekely, L., Kekely, M., Puš, V., & Kořenek, J. (2018). Configurable FPGA packet parser for terabit networks with guaranteed wire-speed throughput. ACM/SIGDA Int. Symp. Field Program. Gate Arrays, pp. 249–258.

  17. Benácek, P., Pu, V., & Kubátová, H. (2016). P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. In: IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

  18. Puš, V., Kekely, L., & Kořenek, J. (2014). Design methodology of configurable high performance packet parser for FPGA. In: International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

  19. Orosz, P., et al. (2019). FPGA-assisted DPI systems: 100 Gbit/s and beyond. IEEE Comm. Surveys & Tutorials, 21(2), 2015–2040.

    Article  Google Scholar 

  20. Ruiz, M. et al. (2019). Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. In: International Conference on Field Programmable Logic and Applications, pp. 286–292.

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Authors and Affiliations

  1. Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan

    Kai-Sheng Hsu & Chung-An Shen

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  1. Kai-Sheng Hsu
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  2. Chung-An Shen
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Correspondence to Chung-An Shen.

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Hsu, KS., Shen, CA. The design of a configurable and low-latency packet parsing system for communication networks. Telecommun Syst 82, 451–463 (2023). https://doi.org/10.1007/s11235-023-00992-9

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