Abstract
PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms.
Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX’s wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.
Similar content being viewed by others
References
R.B. Lee and M.D. Smith, “Media Processing, a New Design Target,” IEEE Micro, vol. 16, no. 4, 1996, pp. 6–9.
R.B. Lee, “Accelerating Multimedia With Enhanced Microprocessors,” IEEE Micro, vol. 15, no. 2, 1995, pp. 22–32.
R.B. Lee, “Subword Parallelism with MAX-2,” IEEE Micro, vol. 16, no. 4, 1996, pp. 51–59.
G. Kane, PA-RISC 2.0 Architecture, Prentice Hall, 1996.
A. Peleg and U. Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro, vol. 16, no. 4, 1996, pp. 42–50.
Intel, IA-32 Intel Architecture Software Developer“s Manual Volume 2: Instruction Set Reference, available at http://www.intel.com, 2002.
M. Tremblay, J.M. O“Connor, V. Narayanan, and H. Liang, “VIS Speeds New Media Processing,” IEEE Micro, vol. 16, no. 4, 1996, pp. 10–20.
Motorola, AltiVec Technology Programming Environments Manual Revision 2.0, available at http://www.motorola.com, 2002.
Intel, Intel Itanium Architecture Software Developer’s Manual Volume 3: Instruction Set Reference – Revision 2.1, available at http://www.intel.com, 2002.
R.B. Lee, A.M. Fiskiran, and A. Bubshait, “Multimedia Instructions in IA-64,” in Proc. IEEE Int. Conf. Multimedia and Expo (ICME), Aug. 2001, pp. 281–284.
R.B. Lee, “Multimedia Extensions For General-Purpose Processors,” IEEE Workshop on Signal Processing Systems—Design and Implementation (SIPS), Nov. 1997, pp. 9–23.
R.B. Lee and A.M. Fiskiran, “Multimedia Instructions in Microprocessors for Native Signal Processing,” in Programmable Digital Signal Processors: Architecture, Programming, and Applications, Yu Hen Hu (ed.), Marcel Dekker, 2002, pp. 91–145.
R.B. Lee, “Instruction Set Architecture for Multimedia Signal Processing,” in Computer Engineering Handbook, Vojin Oklobdzija (ed.), CRC Press, Jan. 2002, pp. 39–1 to 39–38.
I. Elsen, F. Hartung, U. Horn, M. Kampmann, and L. Peters, “Streaming Technology in 3G Mobile Communication Systems,” IEEE Computer, vol. 34, no. 9, 2001, pp. 46–52.
C. Basoglu, R. Gove, K. Kojima, and J. O’Donnell, “Single-Chip Processor For Media Applications: The MAP1000,” Int. Journal of Imaging Systems and Technology, vol. 10, no. 1, 1999, pp. 96–106.
S. Rathnam and G. Slavenburg, “Processing the New World of Interactive Media,” IEEE Signal Processing Magazine, vol. 15, no. 2, 1998, pp. 108–117.
R.B. Lee, A.M. Fiskiran, Z. Shi, and X. Yang, “Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments,” in Proc. Int. Conf. Application-Specific Systems, Architectures, and Processors (ASAP), July. 2002, pp. 253–264.
R.B. Lee, et al., PLX Project at Princeton University, http://palms.ee.princeton.edu/plx.
R.B. Lee, “Efficiency of MicroSIMD Architectures and Index-Mapped Data for Media Processors,” in Proc. Media Processors IS&T/SPIE Symp. Electric Imaging: Science and Technology, Jan. 1999, pp. 34–46.
Z. Luo and R.B. Lee, “Cost-Effective Multiplication with Enhanced Adders for Multimedia Applications,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, 2000, pp. 651–654.
R.B. Lee, “Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures,” in Proc. IEEE Int. Conf. Application-Specific Systems, Architectures, and Processors (ASAP), July. 2000, pp. 3–14.
Y. Arai, T. Agui, and M. Nakajima, “A Fast DCT-SQ Scheme for Images,” Trans. IEICE, vol. E71, no. 11, 1988, pp. 1095–1097.
V. Bhaskaran, K. Konstantinides, R.B. Lee, and J.P. Beck, “Algorithmic and Architectural Enhancements for Real-Time MPEG-1 Decoding on a General Purpose RISC Workstation,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 5, 1995, pp. 380–386.
IEC 14496-2, “Coding of Audio-Visual Objects: Visual, Final Draft International Standard ISO/IEC JTCI/SC29/WG11 N2502,” Oct. 1998.
E.A. Edirisinghe, J. Jiang, and C. Grecos, “Object Boundary Padding Technique for Improving MPEG-4 Compression Efficiency,” IEEE Electronics Letters, vol. 35, no. 17, 1999, pp. 1453–1455.
Y. Liang and B.A. Barsky, “An Analysis and Algorithm for Polygon Clipping,” Communications of the ACM, vol. 26, no. 11, 1983, pp. 868–877.
J.C. Russ, The Image Processing Handbook, CRC Press, 2002.
P. Kolte, R. Smith, and W. Su, “A Fast Median Filter Using AltiVec,” in Proc. Int. Conf. Computer Design (ICCD), Oct. 1999, pp. 384–391.
C.W. Fraser and D. Hanson, A Retargetable C Compiler: Design and Implementation, Addison-Wesley, 1995.
D. Burger and T.M. Austin, “The SimpleScalar Tool Set Version 2.0,” University of Wisconsin-Madison Computer Sciences Department Technical Reportn #1342, June. 1997.
Author information
Authors and Affiliations
Corresponding author
Additional information
Ruby B. Lee is the Forrest G. Hamrick Professor of Engineering and Professor of Electrical Engineering at Princeton University, with an affiliated appointment in the Computer Science department. She is the founder and director of the Princeton Architecture Laboratory for Multimedia and Security (PALMS). Her current research is in rethinking computer architecture for high-performance but low-cost security and multimedia processing. Prior to joining the Princeton faculty in 1998, Dr. Lee served as chief architect at Hewlett-Packard, responsible at different times for processor architecture, multimedia architecture, and security architecture for e-commerce and extended enterprises. She was a key architect in the initial definition and the evolution of the PA-RISC processor architecture used in HP servers and workstations. As chief architect for HP’s multimedia architecture team, Dr. Lee led an inter-disciplinary team focused on architecture to facilitate pervasive multimedia information processing using general-purpose computers. She introduced innovative multimedia instruction set architecture (MAX and MAX-2) in microprocessors, resulting in the industry’s first real-time, high-fidelity MPEG video and audio player implemented in software on low-end desktop computers. Dr. Lee also co-led an HP-Intel multimedia architecture team for IA-64, released in Intel’s Itanium microprocessors. Concurrent with full-time employment at HP, Dr. Lee also served as Consulting Professor of Electrical Engineering at Stanford University. Dr. Lee has a Ph.D. in Electrical Engineering and a M.S. in Computer Science, both from Stanford University, and an A.B. from Cornell University, where she was a College Scholar. She is a Fellow of ACM, a Fellow of IEEE, and a member of IS&T, Phi Beta Kappa, and Alpha Lambda Delta. She has been granted 115 U.S. and international patents, with several patent applications pending.
A. Murat Fiskiran is a Ph. D. student at the Department of Electrical Engineering at Princeton University. He is a member of the Princeton Architecture Laboratory for Multimedia and Security (PALMS) and a Kodak Fellow. His research interests include computer architecture and computer security.
Rights and permissions
About this article
Cite this article
Lee, R.B., Fiskiran, A.M. PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. J VLSI Sign Process Syst Sign Image Video Technol 40, 85–108 (2005). https://doi.org/10.1007/s11265-005-4940-8
Received:
Revised:
Accepted:
Issue Date:
DOI: https://doi.org/10.1007/s11265-005-4940-8