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Reviewing 4-to-2 Adders for Multi-Operand Addition

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Abstract

Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be superior to other types. This paper analyses a recent proposal of various 3- and 4-element redundant digit sets for radix 2, signed and unsigned, and compare their implementations using various encodings of the digits and carries. It is shown that theoretically they are equivalent, and differences in their implementations need only be very marginal. Another recent proposal for the use of the digit-set {0,1,2,3}, with a special 3-bit encoding of digits, is analyzed and some optimizations are shown, including the possibility of using a 2-bit encoding, with a quite significant saving in the wiring of a multiplier tree. All these proposed designs are shown to be equivalent to a standard 4-to-2, carry-save adder, except possibly for a few signal inversions.

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References

  1. C.S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, vol. EC-13, 1964, pp. 14–17. Reprinted in [18].

    Google Scholar 

  2. L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Freq., vol. 34, 1965, pp. 349–356. Reprinted in [18].

    Google Scholar 

  3. A. Weinberger, “4-2 Carry-Save Adder Module,” IBM Technical Disclosure Bulletin, vol. 23, 1981.

  4. N. Takagi, H. Yasuura, and S. Yajima, “High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree,” IEEE Transactions on Computers, vol. C-34, no. 9, 1985, pp. 789–796.

    Google Scholar 

  5. S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, and N. Takagi, “Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation,” in Proc. 8th IEEE Symposium on Computer Arithmetic, IEEE Computer Society, 1987, pp. 80–86.

  6. M.D. Ercegovac and T. Lang, “Effective Coding for Fast Redundant Adders using the Radix-2 Digit Set {0,1,2,3},” in Proc. 31st Asilomar Conf. Signals Systems and Computers, pp. 1163–1167, 1997.

  7. D.S. Phatak, T. Goff, and I. Koren, “Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations,” IEEE Transactions on Computers, vol. 50, no. 11, 2001, pp. 1267–1278.

    Google Scholar 

  8. J. Vuillemin, “A Very Fast Multiplication Algorithm for VLSI Implementation,” INTEGRATION, the VLSI Journal, vol. 1, 1983, pp. 39–52. Reprinted in [19].

    Google Scholar 

  9. M.R. Santoro and M.R. Horowitz, “A Pipelined 64 × 64b Iterative Array Multiplier,” in Proc. IEEE International Solid-State Circuit Conference, 1988, pp. 36–37.

  10. Z.J. Mou and F. Jutand, “‘Overturned-Stairs’ Adder Trees and Multiplier Design,” IEEE Transactions on Computers, vol. 41, no. 8, 1992, pp. 940–948.

    Google Scholar 

  11. N. Ohkubo, M. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, “A 4.4 ns CMOS 54 × 54-b Multiplier Using Pass Transistor Multiplexer,” IEEE Journal of Solid State Circuits, vol. 30, no. 3, 1995, pp. 251-257.

    Google Scholar 

  12. V.G. Oklobdzija and D. Villeger, “Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final Adder in CMOS Technology,” IEEE Transactions on VLSI, vol. 3, no. 2, 1995, pp. 292–301.

    Google Scholar 

  13. V.G. Oklobdzija, D. Villeger, and S.S Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transactions on Computers, vol. 45, no. 3, 1996, pp. 294-306.

    Google Scholar 

  14. P.F. Stelling, C.U. Martel, V.G. Oklobdzija, and R. Ravi, “Optimal Circuits for Parallel Multipliers,” IEEE Transactions on Computers, vol. 47, no. 3, 1998, pp. 273-285.

    Google Scholar 

  15. W.-C. Yeh and C.-W Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, vol. 49, no. 7, 2000, pp. 692–701.

    Google Scholar 

  16. P. Kornerup, “Digit-Set Conversions: Generalizations and Applications,” IEEE Transactions on Computers, vol. C-43, no. 6, 1994, pp. 622–629.

    Google Scholar 

  17. T. Aoki, Y. Sawada, and T. Higuchi, “Signed-Weight Arithmetic and its Application to a Field-Programmable Digital Filter Architecture,” IEICE Trans. Electron, vol. E82, no. 9, 1999, pp. 1687–1698.

    Google Scholar 

  18. Earl E. Swartzlander (Ed.), Computer Arithmetic, Vol I. Dowden, Hutchinson and Ross, Inc., 1980. Reprinted by IEEE Computer Society Press, 1990.

    Google Scholar 

  19. Earl E. Swartzlander (Ed.), Computer Arithmetic, Vol II. IEEE Computer Society Press, 1990.

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Authors and Affiliations

  1. Department of Mathematics and Computer Science, University of Southern Denmark, Odense, Denmark

    Peter Kornerup

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  1. Peter Kornerup
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Correspondence to Peter Kornerup.

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This work was supported by the Danish Natural Science Research Council, grant no. 21-00-0679.

Peter Kornerup was born in Aarhus, Denmark, 1939. He received the mag.scient. degree in mathematics from Aarhus University, Denmark, in 1967. After a period with the University Computing Center, from 1969 involved in establishing the computer science curriculum at Aarhus University, where he helped found the Computer Science Department in 1971. Through most of the 70’s and 80’s he served as Chairman of that department. He spent a leave during 1975/76 with the University of Southwestern Louisiana, Lafayette, LA, four months in 1979 and shorter stays in many other years with Southern Methodist University, Dallas, TX, one month with Université de Provence i Marseille in 1996 and two months with Ecole Normale Supérieure de Lyon i 2001. Since 1988 he has been Professor of Computer Science at Odense University, now University of Southern Denmark, where he has also served a period as the Chairman of this department. His interests include compiler construction, microprogramming, computer networks and computer architecture, but in particular his research has been in computer arithmetic and number representations, with applications in cryptology and digital signal processing.

Prof. Kornerup has served on the program committees for numerous IEEE, ACM and other meetings, in particular he has been on the Program Committees for the 4th through the 16th IEEE Symposium on Computer Arithmetic, and served as Program Co-Chair for these symposia in 1983, 1991 and 1999. He has been guest editor for a number of journal special issues, and also served as an associate editor of the IEEE Transactions on Computers during 1991--95. He is a member of the IEEE.

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Kornerup, P. Reviewing 4-to-2 Adders for Multi-Operand Addition. J VLSI Sign Process Syst Sign Image Video Technol 40, 143–152 (2005). https://doi.org/10.1007/s11265-005-4943-5

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  • DOI: https://doi.org/10.1007/s11265-005-4943-5

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