Abstract
The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm2, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
ISO/IEC JTC1/SC29/WG11 N4668, “Overview of the MPEG-4 Standard,” Jeju, March 2002.
P. Pirsch, M. Bereković, H.-J. Stolberg, and J. Jachalsky, “VLSI Architectures for MPEG-4,” in Proc. 2003 International Symposium on VLSI Technology, Systems, and Applications, 2003, pp. 208–212.
M. Takahashi, T. Nishikawa, M. Hamada, T. Takayanagi, et al., “A 60 MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM,” IEEE Journal Solid-State Circuits, vol. 35, no. 11, 2000, pp. 1713–1721.
N. Seshan, “High VelociTI Processing,” in IEEE Signal Processing Mag., 1998, pp. 86–101.
Philips, TriMedia TM-1300 Media Processor Data Book, Sep. 2000.
M. Rudack, M. Redeker, J. Hilgenstock, S. Moch, and J. Castagne, “A Scalable Large Area Integrated Multiprocessor System for Video Applications with Self-Configuration Facilities,” IEEE Design & Test of Computers, vol. 19, no.1, 2002, pp. 6–17.
B. Ackland, A. Anesko, D. Brinthaupt, et al., “A Single-Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, 2000.
M. Bereković, H.-J. Stolberg, M.B. Kulaczewski, P. Pirsch, H. Möller, H. Runge, J. Kneip, and B. Stabernack, “Instruction Set Extensions for MPEG-4 Video,” Journal VLSI Signal Processing Systems, vol. 23, 1999, pp. 27–50.
ARM Ltd., AMBA Specification Rev. 2.0, www.arm.com, May 1999.
J.P. Wittenburg, W. Hinrichs, H. Lieske, H. Kloos, L. Friebe, and P. Pirsch, “HiPAR-DSP—A Scalable Family of High Performance DSP-Cores,” in Proc. of the 13th Annual IEEE International ASIC/SOC Conference, 2000, pp. 92–96.
ISO/IEC 14496-2:2001/Amd 2:2002, “Streaming video profile,” Feb. 2002.
H.-J. Stolberg, M. Berekovic, P. Pirsch, and H. Runge, “The MPEG-4 Advanced Simple Profile—A Complexity Study,” in Proc. 2nd Workshop and Exhibition on MPEG-4, 2001, pp. 33–36.
J. Curlander and R. McDonough, Synthetic aperture radar: Systems and Signal Processing, Wiley-Interscience, 1991.
C. Simon-Klar, L. Friebe, H. Kloos, H. Lieske, W. Hinrichs, and P. Pirsch, “A Multi DSP Board for Real Time SAR Processing using the HiPAR-DSP 16,” in Proceedings of the International Geoscience and Remote Sensing Symposium 2002, 2002, pp. 2750–2752.
C. Basoglu, W. Lee, and J. O’Donnell, “The Equator MAP-CA DSP: An End-to End Broadband Signal Processor VLIW,” IEEE Trans. Circuits Systems Video Technol., vol. 12, no. 8, 2002, pp. 646–659.
DynaPel Systems, Inc., “DynaPel MPEG-4 Video Codec SDK,” Product Brochure, Nov. 2002.
Sigma Designs, “EM8470 Series: MPEG-4 Decoder for Set-top, DVD and Streaming Applications,” Product Brief, 2002.
ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6, “Study of Final Committee Draft of Joint Video Specification (ITU-T Rec. H.264—ISO/IEC 14496-10 AVC),” Awaji, Dec. 2002.
Model 4294 Quad MPC7410 PowerPC VME Processor, Pentek Processor Brochure, 2002, http://www.pentek.com/support/GetOTD.cfm?Filename=procbroc.pdf.
Author information
Authors and Affiliations
Corresponding author
Additional information
Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.
From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.
Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.
Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.
Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.
Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.
Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.
Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.
Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.
Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.
Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.
Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.
Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.
Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.
Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.
Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.
Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.
From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).
Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.
Rights and permissions
About this article
Cite this article
Stolberg, HJ., Bereković, M., Moch, S. et al. HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. J VLSI Sign Process Syst Sign Image Video Technol 41, 9–20 (2005). https://doi.org/10.1007/s11265-005-6247-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11265-005-6247-1