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An Efficient Picture-Rate Up-Converter

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Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.

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Authors and Affiliations

  1. Dept. of Electrical Eng., Eindhoven University of Technology, Den Dolech 2, 5600 MB, Eindhoven, The Netherlands

    Aleksandar Berić

  2. Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands

    Gerard de Haan, Ramanathan Sethuraman & Jef van Meerbergen

Authors
  1. Aleksandar Berić
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  2. Gerard de Haan
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  3. Ramanathan Sethuraman
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  4. Jef van Meerbergen
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Corresponding author

Correspondence to Aleksandar Berić.

Additional information

Aleksandar Berić received the Electrical Engineering Degree in 2001 from the University of Belgrade, Serbia. In 2002, he started his PhD at the University of Eindhoven, Netherlands. His fields of interest are algorithm/architecture co-design of video processing functions, motion estimation algorithms, low-power VLSI systems and processor architectures.

Gerard de Haan received B.Sc., M.Sc., and Ph.D. degrees from Delft University of Technology in 1977, 1979 and 1992 respectively. He joined Philips Research in 1979. Currently he is a Research Fellow in the group Video Processing & Visual Perception of Philips Research Eindhoven and a Professor at the Eindhoven University of Technology. He has a particular interest in algorithms for motion estimation, scan rate conversion, and image enhancement. His work in these areas has resulted in several books, more than 100 scientific papers (www.ics.ele.tue.nl/∼dehaan/publications.html), more than 50 patents, and several commercially available ICs. He was the first place winner in the 1995 and 2002ICCE Outstanding Paper Awards program, the second place winner in 1997 and in 1998, and the 1998recipient of the Gilles Holst Award. In 2002, he received the Chester Sall Award from the IEEE Consumer Electronics Society. The Philips ‘Natural Motion Television’ concept, based on his PhD-study received the European Innovation Award of the Year 95/96 from the European Imaging and Sound Association, its successor ‘Digital Natural Motion’ received a Wall Street Journal Europe Business Innovation Award 2001. Gerard de Haan is a Senior Member of the IEEE.

Ramanathan Sethuraman is senior scientist in the ESAS Group of Philips Research. He has a MSc in electrical engineering (‘92), and a PhD in electrical engineering (‘97) from the Indian Institute of Science for which he received the best MSc and PhD thesis awards at the Indian Institute of Science. His research interests include embedded system design, low-power VLSI systems, hardware-software co-design, VLSI systems for multimedia, VLSI signal processing and RISC/VLIW processor architectures. He has published more than 40 articles and has 20 patent filings. He has supervised 1 Ph.D student and 4 M.Sc students.

Jef van Meerbergen received the Electrical Engineering Degree and the Ph. D. degree from the Katholieke Universiteit Leuven, Belgium, in 1975 and 1980, respectively. In 1979 he joined the Philips Research Laboratories in Eindhoven, the Netherlands where he started to design MOS digital circuits, domain-specific processors and general-purpose digital signal processors. He was the project leader of the Sigma-Pi project which delivered the first general purpose DSP within Philips.

In 1985 he started working on application-driven high-level synthesis in the context of a European project in close cooperation with Imec. Initially this work was targeted towards DSP applications and resulted in the AR|T system which is used to design audio, video and communication functions.

Later the application domain shifted towards high-throughput streaming applications for which the Phideo compiler was developed. This compiler was used for the design of feature box ICs for 100 Hz conversion for TV (Melzonic, Falconic) and for MPEG2 encoding (I.McIC). The Phideo paper received the best paper award at the 1997 ED&TC conference.

His current interests are in design methods, heterogeneous multiprocessor systems, reconfigurable architectures and Networks-on-Silicon. Jef van Meerbergen is a Philips Research Fellow and Associate Editor of “Design Automation for Embedded Systems”. He is a part-time professor at the Eindhoven University of Technology.

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Berić, A., Haan, G.d., Sethuraman, R. et al. An Efficient Picture-Rate Up-Converter. J VLSI Sign Process Syst Sign Image Video Technol 41, 49–63 (2005). https://doi.org/10.1007/s11265-005-6250-6

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  • DOI: https://doi.org/10.1007/s11265-005-6250-6

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